Inventor

YELURI SHARADA

US25 patents

⚠️ This page may combine multiple inventors who share the name “YELURI SHARADA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YELURI SHARADA

JUNIPER NETWORKS INC

Maintaining data unit order in a network switching device

Scheduler systems and methods for transmit system interfaces

Flow control systems and methods for multi-level buffering schemes

Merge systems and methods for transmit systems interfaces

Micro SID packet processing

Scheduler for transmit system interfaces

Flow control for multi-level buffering schemes

Flow control systems and methods for multi-level buffering schemes

Micro SID packet processing

Use of cache to reduce memory bandwidth pressure with processing pipeline

Micro SID packet processing

Scheduler for transmit system interfaces

SUN MICROSYSTEMS INC

Local stall control method and structure in a microprocessor

Sending both a load instruction and retrieved data from a load buffer to an annex prior to forwarding the load data to register file

Index-based scoreboarding system and method

Forwarding load data to younger instructions in annex

FRAILONG JEAN-MARC

Hardware support for instruction set emulation

System and method for efficient packet replication

Maintaining data unit order in a network switching device

LIBBY JEFFREY G

Fast execution of branch instruction with multiple conditional expressions using programmable branch offset table

System and method for independent synchronous and asynchronous transaction requests

Emulation of multiple instruction sets

HUANG JIANHUI

Use of cache to reduce memory bandwidth pressure with processing pipeline

YELURI SHARADA

Merge systems and methods for transmit system interfaces

GUPTA ANURAG P

Branching to target address by adding value selected from programmable offset table to base address specified in branch instruction