Inventor
IKEJIMA HIROSHI
CN24 patents
⚠️ This page may combine multiple inventors who share the name “IKEJIMA HIROSHI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
SASAKI YOSHITAKA
17 patentsUS8618646B2Dec 31, 2013
Layered chip package and method of manufacturing same
SASAKI YOSHITAKA32 citations92
US8462482B2Jun 11, 2013
Ceramic capacitor and method of manufacturing same
SASAKI YOSHITAKA7 citations84
US8203215B2Jun 19, 2012
Layered chip package and method of manufacturing same
SASAKI YOSHITAKA8 citations84
US8154116B2Apr 10, 2012
Layered chip package with heat sink
SASAKI YOSHITAKA11 citations84
US8653639B2Feb 18, 2014
Layered chip package and method of manufacturing same
SASAKI YOSHITAKA2 citations63
US8466562B2Jun 18, 2013
Layered chip package
SASAKI YOSHITAKA2 citations63
US8432662B2Apr 30, 2013
Ceramic capacitor and method of manufacturing same
SASAKI YOSHITAKA4 citations63
US8421243B2Apr 16, 2013
Layered chip package and method of manufacturing same
SASAKI YOSHITAKA2 citations63
US8203216B2Jun 19, 2012
Layered chip package and method of manufacturing same
SASAKI YOSHITAKA5 citations63
US8171607B2May 8, 2012
Method of manufacturing ceramic capacitor
SASAKI YOSHITAKA2 citations63
US8324741B2Dec 4, 2012
Layered chip package with wiring on the side surfaces
SASAKI YOSHITAKA3 citations62
US8513034B2Aug 20, 2013
Method of manufacturing layered chip package
SASAKI YOSHITAKA0 citations52
US8426979B2Apr 23, 2013
Composite layered chip package
SASAKI YOSHITAKA1 citations52
US8253257B2Aug 28, 2012
Layered chip package and method of manufacturing the same
SASAKI YOSHITAKA1 citations52
US8652877B2Feb 18, 2014
Method of manufacturing layered chip package
SASAKI YOSHITAKA0 citations42
US8541887B2Sep 24, 2013
Layered chip package and method of manufacturing same
SASAKI YOSHITAKA0 citations42
US8441112B2May 14, 2013
Method of manufacturing layered chip package
SASAKI YOSHITAKA0 citations42
HEADWAY TECHNOLOGIES INC
7 patentsUS7968374B2Jun 28, 2011
Layered chip package with wiring on the side surfaces
HEADWAY TECHNOLOGIES INC17 citations92
US7964976B2Jun 21, 2011
Layered chip package and method of manufacturing same
HEADWAY TECHNOLOGIES INC8 citations84
US7915083B1Mar 29, 2011
Method of manufacturing layered chip package
HEADWAY TECHNOLOGIES INC8 citations84
US7902677B1Mar 8, 2011
Composite layered chip package and method of manufacturing same
HEADWAY TECHNOLOGIES INC17 citations84
US8362602B2Jan 29, 2013
Layered chip package and method of manufacturing same
HEADWAY TECHNOLOGIES INC6 citations73
US8358015B2Jan 22, 2013
Layered chip package and method of manufacturing same
HEADWAY TECHNOLOGIES INC4 citations63
US8344494B2Jan 1, 2013
Layered chip package and method of manufacturing same
HEADWAY TECHNOLOGIES INC2 citations63