Inventor
AUGSBURG VICTOR ROBERTS
US24 patents
⚠️ This page may combine multiple inventors who share the name “AUGSBURG VICTOR ROBERTS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
12 patentsUS5996092ANov 30, 1999
System and method for tracing program execution within a processor before and after a triggering event
IBM127 citations98
US6826747B1Nov 30, 2004
System and method for tracing program instructions before and after a trace triggering event within a processor
IBM88 citations97
US6513134B1Jan 28, 2003
System and method for tracing program execution within a superscalar processor
IBM30 citations93
US6826656B2Nov 30, 2004
Reducing power in a snooping cache based multiprocessor environment
IBM35 citations92
US7366877B2Apr 29, 2008
Speculative instruction issue in a simultaneously multithreaded processor
IBM12 citations84
US7035958B2Apr 25, 2006
Re-ordering a first request within a FIFO request queue to a different queue position when the first request receives a retry response from the target
IBM15 citations84
US6834378B2Dec 21, 2004
System on a chip bus with automatic pipeline stage insertion for timing closure
IBM15 citations84
US6948053B2Sep 20, 2005
Efficiently calculating a branch target address
IBM11 citations74
US6816962B2Nov 9, 2004
Re-encoding illegal OP codes into a single illegal OP code to accommodate the extra bits associated with pre-decoded instructions
IBM9 citations74
US6907502B2Jun 14, 2005
Method for moving snoop pushes to the front of a request queue
IBM10 citations73
US6807608B2Oct 19, 2004
Multiprocessor environment supporting variable-sized coherency transactions
IBM2 citations63
US7296175B2Nov 13, 2007
System on a chip bus with automatic pipeline stage insertion for timing closure
IBM1 citations52
QUALCOMM INC
9 patentsUS7587580B2Sep 8, 2009
Power efficient instruction prefetch mechanism
QUALCOMM INC14 citations84
US7426626B2Sep 16, 2008
TLB lock indicator
QUALCOMM INC9 citations84
US7366869B2Apr 29, 2008
Method and system for optimizing translation lookaside buffer entries
QUALCOMM INC15 citations84
US7437537B2Oct 14, 2008
Methods and apparatus for predicting unaligned memory access
QUALCOMM INC7 citations74
US7330941B2Feb 12, 2008
Global modified indicator to reduce power consumption on cache miss
QUALCOMM INC4 citations63
US7725625B2May 25, 2010
Latency insensitive FIFO signaling protocol
QUALCOMM INC2 citations62
US7650466B2Jan 19, 2010
Method and apparatus for managing cache partitioning using a dynamic boundary
QUALCOMM INC3 citations62
US7721067B2May 18, 2010
Translation lookaside buffer manipulation
QUALCOMM INC4 citations61
US7454538B2Nov 18, 2008
Latency insensitive FIFO signaling protocol
QUALCOMM INC0 citations51