Inventor

BRIDGES JEFFREY TODD

US52 patents

⚠️ This page may combine multiple inventors who share the name “BRIDGES JEFFREY TODD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BRIDGES JEFFREY TODD

QUALCOMM INC

System and method of correcting a branch misprediction

System and method wherein conditional instructions unconditionally provide output

Automatic calibration circuits for operational calibration of critical-path time delays in adaptive clock distribution systems, and related methods and systems

Adaptive clock generators, systems, and methods

Power efficient instruction prefetch mechanism

TLB lock indicator

Power saving methods and apparatus to selectively enable cache bits based on known processor state

Pre-decode error handling via branch correction

Method and system for optimizing translation lookaside buffer entries

Method and apparatus for efficiently accessing first and second branch history tables to predict branch instructions

Caching memory attribute indicators with cached memory data field

Adaptive voltage modulation circuits for adjusting supply voltage to reduce supply voltage droops and minimize power consumption

Adaptive voltage scalers (AVSs), systems, and related methods

Methods and apparatus for predicting unaligned memory access

Methods and apparatus for dynamic frequency scaling of phase locked loops for microprocessors

Allocating power between multiple central processing units (CPUs) in a multi-CPU processor based on total current availability and individual CPU quality-of-service (QoS) requirements

Method and system for providing an energy efficient register file

Handling cache miss in an instruction crossing a cache line boundary

Power saving methods and apparatus to selectively enable comparators in a CAM renaming register file based on known processor state

Conditional instruction execution via emissary instruction for condition evaluation

Method and apparatus for managing a return stack

Dynamic pipeline throttling using confidence-based weighting of in-flight branch instructions

Latency insensitive FIFO signaling protocol

Method and apparatus for managing cache partitioning using a dynamic boundary

Circuit and method for subdividing a CAMRAM bank by controlling a virtual ground

Synthesizing intermediate performance levels in integrated circuits, and related processor systems, methods, and computer-readable media

Translation lookaside buffer manipulation

Instruction cache having fixed number of variable length instructions

Methods and apparatus to insure correct predecode

Latency insensitive FIFO signaling protocol

Method and apparatus for dynamic clock and voltage scaling in a computer processor based on program phase

Method and apparatus for dynamic clock and voltage scaling in a computer processor based on program phase

Adaptive voltage scalers (AVSs), systems, and related methods

IBM

Address pipelining for data transfers

System and method for tracing program execution within a processor before and after a triggering event

System and method for tracing program instructions before and after a trace triggering event within a processor

Processor local bus posted DMA FlyBy burst transfers

System and method for program execution tracing within an integrated processor

System and method for tracing program execution within a superscalar processor

Speculative instruction issue in a simultaneously multithreaded processor

Efficiently calculating a branch target address

Re-encoding illegal OP codes into a single illegal OP code to accommodate the extra bits associated with pre-decoded instructions

Methods, cache memories, systems and computer program products for storing transient, normal, and locked entries in an associative cache memory

Sending thread message generated using DCR command pointed message control block storing message and response memory address in multiprocessor

Translation look aside buffer (TLB) with increased translational capacity for multi-threaded computer processes

HOFMANN RICHARD GERARD

Method and apparatus for adaptive voltage scaling based on instruction usage

BRIDGES JEFFREY TODD

Circuits, systems and methods to detect and accommodate power supply voltage droop

DIEFFENDERFER JAMES NORRIS

Early conditional selection of an operand

SARTORIUS THOMAS ANDREW

Power efficient instruction prefetch mechanism

MICHALAK GERALD PAUL

Methods and apparatus for voltage scaling