Inventor · disambiguated record
Larry R. Tate
Also filed as: TATE LARRY · TATE LARRY R
21 granted patents·3 pending applications·318 citations·filing 1988–2013
95Inventor score
Files withINTEL CORP9LUCENT TECHNOLOGIES INC5AGERE SYST GUARDIAN CORP3AGERE SYSTEMS INC1DABRAL SANJAY1
Top patents by PatentIndex Score
24 records- 0188US9465237B2Automatic focus prescription lens eyeglassesINTEL CORP·Filed 2013·Granted Oct 11, 2016·20 cites·23 claims
- 0279US7917828B2Providing error correction coding for probed dataINTEL CORP·Filed 2006·Granted Mar 29, 2011·12 cites·9 claims
- 0377US6029267ASingle-cycle, soft decision, compare-select operation using dual-add processorLUCENT TECHNOLOGIES INC·Filed 1997·Granted Feb 22, 2000·42 cites·15 claims
- 0475US7525723B2Circuit board-to-circuit board connectors having electro-optic modulatorsINTEL CORP·Filed 2006·Granted Apr 28, 2009·7 cites·23 claims
- 0573US7769109B2Method and apparatus to perform modulation using integer timing relationships between intra symbol modulation componentsINTEL CORP·Filed 2008·Granted Aug 3, 2010·0 cites·13 claims
- 0670US7900098B2Receiver for recovering and retiming electromagnetically coupled dataINTEL CORP·Filed 2008·Granted Mar 1, 2011·5 cites·18 claims
- 0767US7605671B2Component-less termination for electromagnetic couplers used in high speed/frequency differential signalingINTEL CORP·Filed 2007·Granted Oct 20, 2009·3 cites·15 claims
- 0866US4967388ATruncated product partial canonical signed digit multiplierHARRIS SEMICONDUCTOR PATENTS·Filed 1988·Granted Oct 30, 1990·36 cites·10 claims
- 0963US5889689AHierarchical carry-select, three-input saturationLUCENT TECHNOLOGIES INC·Filed 1997·Granted Mar 30, 1999·43 cites·17 claims
- 1062US7480330B2Method and apparatus to perform modulation using integer timing relationships between intra symbol modulation componentsINTEL CORP·Filed 2004·Granted Jan 20, 2009·0 cites·13 claims
- 1160US7660349B2Transmit equalizer compensation for probe receiversINTEL CORP·Filed 2005·Granted Feb 9, 2010·1 cites·16 claims
- 1260US7342969B2Signaling with multiple clocksINTEL CORP·Filed 2003·Granted Mar 11, 2008·6 cites·33 claims
- 1359US6446193B1Method and apparatus for single cycle processing of data associated with separate accumulators in a dual multiply-accumulate architectureAGERE SYST GUARDIAN CORP·Filed 1997·Granted Sep 3, 2002·35 cites·24 claims
- 1456US9054902B2Apparatus and system for switching equalizationSONG SANQUAN·Filed 2012·Granted Jun 9, 2015·1 cites·16 claims
- 1555US6530014B2Near-orthogonal dual-MAC instruction set architecture with minimal encoding bitsAGERE SYSTEMS INC·Filed 1998·Granted Mar 4, 2003·30 cites·14 claims
- 1650US6272188B1Single-cycle accelerator for extremun state searchAGERE SYST GUARDIAN CORP·Filed 1998·Granted Aug 7, 2001·14 cites·24 claims
- 1748US8428114B2Transmit equalizer compensation for probe receiversTATE LARRY R·Filed 2009·Granted Apr 23, 2013·0 cites·21 claims
- 1845US6073228AModulo address generator for generating an updated addressLUCENT TECHNOLOGIES INC·Filed 1997·Granted Jun 6, 2000·22 cites·15 claims
- 1944US6009128AMetric acceleration on dual MAC processorLUCENT TECHNOLOGIES INC·Filed 1997·Granted Dec 28, 1999·10 cites·13 claims
- 2043US6467035B2System and method for performing table look-ups using a multiple data fetch architectureAGERE SYST GUARDIAN CORP·Filed 1997·Granted Oct 15, 2002·16 cites·13 claims
- 2141US6115805ANon-aligned double word fetch bufferLUCENT TECHNOLOGIES INC·Filed 1998·Granted Sep 5, 2000·15 cites·18 claims
- 2238US2009085697A1Method and apparatus for analog validation of high speed buses using electromagnetic couplersHINCK TODD·Filed 2007·Application pending·0 cites
- 2337US2008122463A1Testing microelectronic devices using electro-optic modulator probesDABRAL SANJAY·Filed 2006·Application pending·0 cites
- 2433US2003036259A1High speed, low latency bus modulation method and apparatus including a semiconductor structure for implementing sameMOTOROLA INC·Filed 2001·Application pending·0 cites
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