Inventor

SENGUPTA RWIK

US43 patents

⚠️ This page may combine multiple inventors who share the name “SENGUPTA RWIK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SENGUPTA RWIK

SAMSUNG ELECTRONICS CO LTD

Semiconductor device having buried power rail

Integrated circuits with Si and non-Si nanosheet FET co-integration with low band-to-band tunneling and methods of fabricating the same

Nanosheet FETs with stacked nanosheets having smaller horizontal spacing than vertical spacing for large effective width

Multi-bit, SoC-compatible neuromorphic weight cell using ferroelectric FETs

Apparatus and method of forming backside buried conductor in integrated circuit

Semiconductor device and method for making the same

Stacked independently contacted field effect transistor having electrically separated first and second gates

Multiple channel length finFETs with same physical gate length

Gate-all-around field effect transistors with horizontal nanosheet conductive channel structures for MOL/inter-channel spacing and related cell architectures

Flip-flop layout architecture implementation for semiconductor device

Power distribution network using buried power rail

Dielectric separation of partial GAA FETs

Method for forming low parasitic capacitance source and drain contacts

VFET standard cell architecture with improved contact and super via

Integrated circuit including field effect transistors having a contact on active gate compatible with a small cell area having a small contacted poly pitch

Method and system for providing a reverse-engineering resistant hardware embedded security module

Semiconductor device including a repeater/buffer at higher metal routing layers and methods of manufacturing the same

Semiconductor devices including finFETs and local interconnect layers and methods of fabricating the same

Unipolar complementary logic

Semiconductor device

Semiconductor cell blocks having non-integer multiple of cell heights

Power rail for standard cell block

Semiconductor device and method of forming the same

VFET standard cell architecture with improved contact and super via

Multi-bit, SoC-compatible neuromorphic weight cell using ferroelectric FETs

4T4R ternary weight cell with high on/off ratio background

Method and system for providing a reverse engineering resistant hardware embedded security module

Integrated circuit including field effect transistors having a contact on active gate compatible with a small cell area having a small contacted poly pitch

System and method for efficient enhancement of an on/off ratio of a bitcell based on 3T2R binary weight cell with spin orbit torque MJTs (SOT-MTJs)

Sub 59 MV/decade SI CMOS compatible tunnel FET as footer transistor for power gating

Methods of forming defect-free SRB onto lattice-mismatched substrates and defect-free fins on insulators

2T2R binary weight cell with high on/off ratio background

Variation resistant 3T3R binary weight cell with low output current and high on/off ratio

Semiconductor device

Semiconductor cell blocks having non-integer multiple of cell heights

Nanosheet field effect transistor cell architecture

Metal oxysilicate diffusion barriers for damascene metallization with low RC delays and methods for forming the same

CADENCE DESIGN SYSTEMS INC

Electronic design tracing and tamper detection using automatically generated layout patterns

Context-aware circuit design layout construct

System and method for device placement

SENGUPTA RWIK

Semiconductor device with an isolation gate and method of forming

Standard cell for integrated circuit

KITTL JORGE A

Methods of forming semiconductor devices including conductive contacts on source/drains