Inventor

RODDER MARK

US15 patents

⚠️ This page may combine multiple inventors who share the name “RODDER MARK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SAMSUNG ELECTRONICS CO LTD

14 patents

US9570395B1Feb 14, 2017

Integrated circuit including field effect transistors having a contact on active gate compatible with a small cell area having a small contacted poly pitch

SAMSUNG ELECTRONICS CO LTD5 citations73

US9899529B2Feb 20, 2018

Method to make self-aligned vertical field effect transistor

SAMSUNG ELECTRONICS CO LTD5 citations72

US9870940B2Jan 16, 2018

Methods of forming nanosheets on lattice mismatched substrates

SAMSUNG ELECTRONICS CO LTD5 citations72

US11211493B2Dec 28, 2021

Apparatus and method of modulating threshold voltage for fin field effect transistor (FinFET) and nanosheet FET

SAMSUNG ELECTRONICS CO LTD0 citations62

US11158738B2Oct 26, 2021

Method of forming isolation dielectrics for stacked field effect transistors (FETs)

SAMSUNG ELECTRONICS CO LTD1 citations62

US10861950B2Dec 8, 2020

Integrated circuit including field effect transistors having a contact on active gate compatible with a small cell area having a small contacted poly pitch

SAMSUNG ELECTRONICS CO LTD1 citations62

US10181527B2Jan 15, 2019

FinFet having dual vertical spacer and method of manufacturing the same

SAMSUNG ELECTRONICS CO LTD1 citations62

US10424581B2Sep 24, 2019

Sub 59 MV/decade SI CMOS compatible tunnel FET as footer transistor for power gating

SAMSUNG ELECTRONICS CO LTD0 citations52

US9773904B2Sep 26, 2017

Vertical field effect transistor with biaxial stressor layer

SAMSUNG ELECTRONICS CO LTD0 citations47

US10510665B2Dec 17, 2019

Low-k dielectric pore sealant and metal-diffusion barrier formed by doping and method for forming the same

SAMSUNG ELECTRONICS CO LTD0 citations40

US9728502B2Aug 8, 2017

Metal oxysilicate diffusion barriers for damascene metallization with low RC delays and methods for forming the same

SAMSUNG ELECTRONICS CO LTD0 citations40

TEXAS INSTRUMENTS INC

1 patent

US7163878B2Jan 16, 2007

Ultra-shallow arsenic junction formation in silicon germanium

TEXAS INSTRUMENTS INC6 citations71

RODDER MARK

SAMSUNG ELECTRONICS CO LTD

Semiconductor device having buried power rail

Horizontal nanosheet FETs and methods of manufacturing the same

S/D connection to individual channel layers in a nanosheet FET

Integrated circuit including field effect transistors having a contact on active gate compatible with a small cell area having a small contacted poly pitch

Method to make self-aligned vertical field effect transistor

Methods of forming nanosheets on lattice mismatched substrates

Apparatus and method of modulating threshold voltage for fin field effect transistor (FinFET) and nanosheet FET

Method of forming isolation dielectrics for stacked field effect transistors (FETs)

Integrated circuit including field effect transistors having a contact on active gate compatible with a small cell area having a small contacted poly pitch

FinFet having dual vertical spacer and method of manufacturing the same

Sub 59 MV/decade SI CMOS compatible tunnel FET as footer transistor for power gating

Vertical field effect transistor with biaxial stressor layer

Low-k dielectric pore sealant and metal-diffusion barrier formed by doping and method for forming the same

Metal oxysilicate diffusion barriers for damascene metallization with low RC delays and methods for forming the same

TEXAS INSTRUMENTS INC

Ultra-shallow arsenic junction formation in silicon germanium