Inventor

BLASCO-ALLUE CONRADO

US23 patents

⚠️ This page may combine multiple inventors who share the name “BLASCO-ALLUE CONRADO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BLASCO-ALLUE CONRADO

ADVANCED RISC MACH LTD

Apparatus and method for facilitating debugging of sequences of processing instructions using context identifier comparison

Integrated circuit and method of operation of such a circuit employing serial test scan chains

Renaming wide register source operand with plural short register source operands for select instructions to detect dependency fast with existing mechanism

Diagnostic mechanisms within multi processing systems

Decoding predication instructions within a superscaler data processing system

Forced diagnostic entry upon power-up

Multiple instruction set decoding

Provision of debug via a separate ring bus in a data processing apparatus

APPLE INC

Multi-level dispatch for a superscalar processor

Usefulness indication for indirect branch prediction training

IT instruction pre-decode

Next fetch predictor return address stack

RDA checkpoint optimization

Mechanism for reducing cache power consumption using cache way prediction

Arithmetic branch fusion

BLASCO-ALLUE CONRADO

Fetch width predictor

Methods, apparatus, and processors for packing multiple iterations of loop in a loop buffer

Loop buffer learning

KELLER JAMES B

Zero cycle move

Optimizing register initialization operations

GUPTA SANDEEP

Instruction set architecture mode dependent sub-size access of register with associated status indication

HARDAGE JAMES NOLAN

Size mis-match hazard detection

ARM LIMTED

Memory self-test via a ring bus in a data processing apparatus