Inventor

JU DZ-CHING

US32 patents

⚠️ This page may combine multiple inventors who share the name “JU DZ-CHING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JU DZ-CHING

INTEL CORP

Automatic generation of software-controlled caching and ordered synchronization

Compiler-directed speculative approach to resolve performance-degrading long latency events in an application

Incorporating trigger loads in branch histories for branch prediction

Least critical used replacement with critical cache

Methods and systems for integrated scheduling and resource management for a compiler

Critical loads guided data prefetching

Allocating call stack frame entries at different memory levels to functions in a program

Software caching with bounded-error delayed update

Runtime critical load/data ordering

Methods and apparatus for preserving precise exceptions in code reordering by using control speculation

Function unit based finite state automata data structure, transitions and methods for making the same

HEWLETT PACKARD CO

Unified compiler framework for control and data speculation with recovery code

Global control flow treatment of predicated code

Method and system for eliminating phi instruction resource interferences and redundant copy instructions from static-single-assignment-form computer code

Apparatus and method for incrementally update static single assignment form for cloned variable name definitions

System and method for solving general global data flow predicated code problems

IBM

Method of, system for, and computer program product for providing efficient utilization of memory hierarchy through code restructuring

Method of, system for, and computer program product for providing efficient utilization of memory hierarchy through code restructuring

Method of, system for, and computer program product for providing quick fusion in WHERE constructs

Method of, system for, and computer program product for providing inlined nested array constructors using normalized counters

HEWLETT PACKARD DEVELOPMENT CO

System and method for efficiently passing information between compiler and post-compile-time software

Method and apparatus for ordered predicate phi in static single assignment form

NVIDIA CORP

Techniques for parallel execution

Kernel generation for neural networks

MEDIATEK INC

Memory management method for supporting shared virtual memories with hybrid page table utilization and related machine readable medium

System and method for managing static divergence in a SIMD computing architecture

HEWLETT PACKARD DEVELOPMENT LP

Data speculation within modulo scheduled loops

BRETERNITZ MAURICIO

Automatic kernel migration for heterogeneous cores

ADVANCED MICRO DEVICES INC

Method and system for data prefetching for loops based on linear induction expressions

YE MEI

Proactive loop fusion of non-adjacent loops with intervening control flow instructions

LI XIAO-FENG

High performance queue implementations in multiprocessor systems

JU DZ-CHING

Methods and apparatus for preserving precise exceptions in code reordering by using control speculation