Inventor

GENDEN MICHAEL J

US37 patents

⚠️ This page may combine multiple inventors who share the name “GENDEN MICHAEL J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GENDEN MICHAEL J

IBM

Managing an issue queue for fused instructions and paired instructions in a microprocessor

Managing an issue queue for fused instructions and paired instructions in a microprocessor

Distributed history buffer flush and restore handling in a parallel slice design

Distributed history buffer flush and restore handling in a parallel slice design

Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor

Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor

Multi-slice processor issue of a dependent instruction in an issue queue based on issue of a producer instruction

Dual compare of least-significant-bit for dependency wake up from a fused instruction tag in a microprocessor

Merging status and control data in a reservation station

Mechanism for using a reservation station as a scratch register

Tagging target branch predictors with context with index modification and late stop fetch on tag mismatch

Low latency execution of floating-point record form instructions

Parallel dispatching of multi-operation instructions in a multi-slice computer processor

Parallel dispatching of multi-operation instructions in a multi-slice computer processor

Prioritization protocols of conditional branch instructions

Managing an issue queue for fused instructions and paired instructions in a microprocessor

Managing an issue queue for fused instructions and paired instructions in a microprocessor

History buffer with single snoop tag for multiple-field registers

History buffer with hybrid entry support for multiple-field registers

Universal history buffer to support multiple register types

History buffer for multiple-field registers

Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor core

Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor core

Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor

Operation of a multi-slice processor with selective producer instruction types

Operation of a multi-slice processor with selective producer instruction types

Operation of a multi-slice processor with selective producer instruction types

Operation of a multi-slice processor with selective producer instruction types

Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor

Low latency execution of floating-point record form instructions

Low latency execution of floating-point record form instructions

Cracked execution of move-to-FPSCR instructions

Region-weighted accounting of multi-threaded processor core according to dispatch state

Decoupling of conditional branches

Multi-slice processor issue of a dependent instruction in an issue queue based on issue of a producer instruction

Shared compare lanes for dependency wake up in a pair-based issue queue

BISHOP JAMES WILSON

Region-weighted accounting of multi-threaded processor core according to dispatch state