Inventor
WARD KENNETH L
US27 patents
⚠️ This page may combine multiple inventors who share the name “WARD KENNETH L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
26 patentsUS7526583B2Apr 28, 2009
Method and apparatus to launch write queue read data in a microprocessor recovery unit
IBM8 citations82
US11119772B2Sep 14, 2021
Check pointing of accumulator register results in a microprocessor
IBM3 citations73
US10901743B2Jan 26, 2021
Speculative execution of both paths of a weakly predicted branch instruction
IBM2 citations73
US9798549B1Oct 24, 2017
Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction
IBM3 citations72
US11086630B1Aug 10, 2021
Finish exception handling of an instruction completion table
IBM3 citations69
US11366671B2Jun 21, 2022
Completion mechanism for a microprocessor instruction completion table
IBM0 citations62
US10929144B2Feb 23, 2021
Speculatively releasing store data before store instruction completion in a processor
IBM0 citations62
US10761856B2Sep 1, 2020
Instruction completion table containing entries that share instruction tags
IBM1 citations62
US10423423B2Sep 24, 2019
Efficiently managing speculative finish tracking and error handling for load instructions
IBM1 citations62
US11327757B2May 10, 2022
Processor providing intelligent management of values buffered in overlaid architected and non-architected register files
IBM0 citations61
US7603497B2Oct 13, 2009
Method and apparatus to launch write queue read data in a microprocessor recovery unit
IBM2 citations61
US10877763B2Dec 29, 2020
Dispatching, allocating, and deallocating instructions with real/virtual and region tags in a queue in a processor
IBM0 citations52
US10108423B2Oct 23, 2018
History buffer with single snoop tag for multiple-field registers
IBM1 citations52
US9996353B2Jun 12, 2018
Universal history buffer to support multiple register types
IBM1 citations52
US9971604B2May 15, 2018
History buffer for multiple-field registers
IBM1 citations52
US11269647B2Mar 8, 2022
Finish status reporting for a simultaneous multithreading processor using an instruction completion table
IBM0 citations51
US11068274B2Jul 20, 2021
Prioritized instructions in an instruction completion table of a simultaneous multithreading processor
IBM0 citations51
US10977034B2Apr 13, 2021
Instruction completion table with ready-to-complete vector
IBM0 citations51
US10831489B2Nov 10, 2020
Mechanism for completing atomic instructions in a microprocessor
IBM0 citations51
US10725786B2Jul 28, 2020
Completion mechanism for a microprocessor instruction completion table
IBM0 citations51
US10713057B2Jul 14, 2020
Mechanism to stop completions using stop codes in an instruction completion table
IBM0 citations51
US10552165B2Feb 4, 2020
Efficiently managing speculative finish tracking and error handling for load instructions
IBM0 citations51
US10169046B2Jan 1, 2019
Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction
IBM0 citations51
US11030018B2Jun 8, 2021
On-demand multi-tiered hang buster for SMT microprocessor
IBM0 citations49
US9971687B2May 15, 2018
Operation of a multi-slice processor with history buffers storing transaction memory state information
IBM0 citations41
US10831492B2Nov 10, 2020
Most favored branch issue
IBM0 citations39