Inventor
DUNNING DAVID S
US56 patents
⚠️ This page may combine multiple inventors who share the name “DUNNING DAVID S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
47 patentsUS6333929B1Dec 25, 2001
Packet format for a distributed system
INTEL CORP159 citations99
US7313712B2Dec 25, 2007
Link power saving state
INTEL CORP71 citations98
US6683850B1Jan 27, 2004
Method and apparatus for controlling the flow of data between servers
INTEL CORP108 citations98
US6343067B1Jan 29, 2002
Method and apparatus for failure and recovery in a computer network
INTEL CORP130 citations98
US6181704B1Jan 30, 2001
Method and apparatus for input/output link retry, failure and recovery in a computer network
INTEL CORP123 citations98
US6170025B1Jan 2, 2001
Distributed computer system supporting remote interrupts and lock mechanism
INTEL CORP128 citations98
US6606360B1Aug 12, 2003
Method and apparatus for receiving data
INTEL CORP86 citations97
US5898826AApr 27, 1999
Method and apparatus for deadlock-free routing around an unusable routing component in an N-dimensional network
INTEL CORP126 citations96
US6760307B2Jul 6, 2004
Method and apparatus for controlling the flow of data between servers using optimistic transmitter
INTEL CORP54 citations95
US7324458B2Jan 29, 2008
Physical layer loopback
INTEL CORP28 citations93
US6646991B1Nov 11, 2003
Multi-link extensions and bundle skew management
INTEL CORP22 citations93
US6094683AJul 25, 2000
Link bundling in a network
INTEL CORP41 citations93
US7957428B2Jun 7, 2011
Methods and apparatuses to effect a variable-width link
INTEL CORP26 citations92
US7610500B2Oct 27, 2009
Link power saving state
INTEL CORP17 citations92
US7209907B2Apr 24, 2007
Method and apparatus for periodically retraining a serial links interface
INTEL CORP18 citations92
US7203853B2Apr 10, 2007
Apparatus and method for low latency power management on a serial data link
INTEL CORP31 citations92
US6765975B2Jul 20, 2004
Method and apparatus for a tracking data receiver compensating for deterministic jitter
INTEL CORP25 citations92
US7054374B1May 30, 2006
Differential simultaneous bi-directional receiver
INTEL CORP27 citations91
US6647423B2Nov 11, 2003
Direct message transfer between distributed processes
INTEL CORP41 citations89
US7936684B2May 3, 2011
Physical layer loopback
INTEL CORP10 citations84
US7844767B2Nov 30, 2010
Method for identifying bad lanes and exchanging width capabilities of two CSI agents connected across a link
INTEL CORP10 citations84
US7711878B2May 4, 2010
Method and apparatus for acknowledgement-based handshake mechanism for interactively training links
INTEL CORP12 citations84
US7633877B2Dec 15, 2009
Method and apparatus for meeting compliance for debugging and testing a multi-speed, point-to-point link
INTEL CORP15 citations84
US7366964B2Apr 29, 2008
Method, system, and apparatus for loopback entry and exit
INTEL CORP10 citations84
US7219220B2May 15, 2007
Methods and apparatuses for resetting the physical layers of two agents interconnected through a link-based interconnection
INTEL CORP16 citations84
US7203872B2Apr 10, 2007
Cache based physical layer self test
INTEL CORP14 citations84
US9992135B2Jun 5, 2018
Apparatus and method for fusion of compute and switching functions of exascale system into a single component by using configurable network-on-chip fabric with distributed dual mode input-output ports and programmable network interfaces
INTEL CORP9 citations83
US9287208B1Mar 15, 2016
Architecture for on-die interconnect
INTEL CORP8 citations83
US7328359B2Feb 5, 2008
Technique to create link determinism
INTEL CORP9 citations83
US6446235B1Sep 3, 2002
Cumulative error detecting code
INTEL CORP18 citations83
US7586951B2Sep 8, 2009
Method, apparatus, and system for idle state definition for power management
INTEL CORP8 citations82
US6781434B2Aug 24, 2004
Low charge-dump transistor switch
INTEL CORP15 citations82
US7639701B2Dec 29, 2009
Packet format for a distributed system
INTEL CORP5 citations74
US7206955B2Apr 17, 2007
Bundle skew management and cell synchronization
INTEL CORP7 citations74
US6687840B1Feb 3, 2004
Multi-link extensions and bundle skew management
INTEL CORP12 citations74
US7746795B2Jun 29, 2010
Method, system, and apparatus for loopback parameter exchange
INTEL CORP7 citations73
US7747888B2Jun 29, 2010
Technique to create link determinism
INTEL CORP6 citations73
US7362739B2Apr 22, 2008
Methods and apparatuses for detecting clock failure and establishing an alternate clock lane
INTEL CORP7 citations73
US10712809B2Jul 14, 2020
Link power savings with state retention
INTEL CORP1 citations72
US10175744B2Jan 8, 2019
Link power savings with state retention
INTEL CORP2 citations72
US9998401B2Jun 12, 2018
Architecture for on-die interconnect
INTEL CORP3 citations72
US9588575B2Mar 7, 2017
Link power savings with state retention
INTEL CORP2 citations72
US7280629B2Oct 9, 2007
Method and apparatus for receiving data based on tracking zero crossings
INTEL CORP6 citations72
US6917659B1Jul 12, 2005
Method and apparatus for receiving data
INTEL CORP7 citations72
US7415032B2Aug 19, 2008
Aggregatable connectivity
INTEL CORP7 citations70
US7394766B2Jul 1, 2008
Multi-link extensions and bundle skew management
INTEL CORP4 citations63
US7965741B2Jun 21, 2011
Method, apparatus, and system for idle state definition for power management
INTEL CORP3 citations61
DROTTAR KEN
2 patentsSCHOENBORN THEODORE Z
1 patentShowing the top 50 of 56 patents by PatentIndex Score.