Inventor

JAHAGIRDAR SANJEEV S

US49 patents

⚠️ This page may combine multiple inventors who share the name “JAHAGIRDAR SANJEEV S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JAHAGIRDAR SANJEEV S

INTEL CORP

Controlling power delivery to a processor via a bypass

Method, apparatus, and system for optimizing frequency and performance in a multidie microprocessor

Method, apparatus, and system for optimizing frequency and performance in a multidie microprocessor

Adaptive multibit bus for energy optimization

Controlling power delivery to a processor via a bypass

Controlling power delivery to a processor via a bypass

Controlling power delivery to a processor via a bypass

Adaptive multibit bus for energy optimization

Configurable power supplies for dynamic current sharing

Dynamic precision for neural network compute operations

Dual path sequential element to reduce toggles in data path

Dynamic voltage-frequency curve management

System, method and apparatus for energy efficiency and energy conservation by configuring power management parameters during run time

Asymmetric performance multicore architecture with same instruction set architecture

Controlling power delivery to a processor via a bypass

Adaptive multibit bus for energy optimization

Method, apparatus, and system for energy efficiency and energy conservation including determining an optimal power state of the apparatus based on residency time of non-core domains in a power saving state

Independent control of processor core retention states

Configurable power supplies for dynamic current sharing

Dynamic precision for neural network compute operations

Dynamic voltage-frequency curve mangement

Regional adjustment of render rate

Regional adjustment of render rate

Regional adjustment of render rate

Hybrid low power homogenous grapics processing units

Adaptive multibit bus for energy optimization

Regional adjustment of render rate

Dual path sequential element to reduce toggles in data path

Hybrid low power homogenous grapics processing units

Regional adjustment of render rate

System, method and apparatus for energy efficiency and energy conservation by configuring power management parameters during run time

Power consumption management for communication bus

Dual path sequential element to reduce toggles in data path

Migrating threads between asymmetric cores in a multiple core processor

Asymmetric performance multicore architecture with same instruction set architecture

Regional adjustment of render rate

Power consumption management for communication bus

Hybrid low power homogenous grapics processing units

Local closed loop efficiency control using IP metrics

Dynamic control of liquid cooling pumps to provide thermal cooling uniformity

Method, apparatus, and system for optimizing frequency and performance in a multidie microprocessor

Local closed loop efficiency control using IP metrics

Configurable power supplies for dynamic current sharing

SODHI INDER M

Method, apparatus, and system for energy efficiency and energy conservation including improved processor core deep power down exit latency by using register secondary uninterrupted power supply

Method, apparatus, and system for energy efficiency and energy conservation including dynamic cache sizing and cache operating voltage management for optimal power performance

Method, apparatus, and system for energy efficiency and energy conservation including energy efficient processor thermal throttling using deep power down mode

JAHAGIRDAR SANJEEV S

Migrating threads between asymmetric cores in a multiple core processor

TAHOE RES LTD

Controlling power delivery to a processor via a bypass

GEORGE VARGHESE

Asymmetric performance multicore architecture with same instruction set architecture