Inventor

PUFFER DAVID

US68 patents

⚠️ This page may combine multiple inventors who share the name “PUFFER DAVID”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PUFFER DAVID

INTEL CORP

Apparatus and method for memory management in a graphics processing environment

Memory transaction ordering

Memory controller performing a mid transaction refresh and handling a suspend signal

Graphics processor data access and sharing

Multi-tile memory management

Hierarchical general register file (GRF) for execution block

Assistance for hardware prefetch in cache access

Multi-tile memory management

Engine to enable high speed context switching via on-die storage

Hierarchical general register file (GRF) for execution block

Apparatus and method for memory management in a graphics processing environment

Sector cache for compression

Thread prefetch mechanism

Engine to enable high speed context switching via on-die storage

System, apparatus and method for multi-die distributed memory mapped input/output support

Apparatus and method for memory management in a graphics processing environment

Cache and compression interoperability in a graphics processor pipeline

Coarse grain coherency

Page faulting and selective preemption

Multi-tile memory management

Scalable I/O virtualization interrupt and scheduling

Control flow mechanism for execution of graphics processor instructions using active channel packing

Sector cache for compression

Isochronous agent data pinning in a multi-level memory system

Graphics processor register file including a low energy portion and a high capacity portion

Page faulting and selective preemption

Page faulting and selective preemption

Sector cache for compression

Sector cache for compression

Sector cache for compression

Page faulting and selective preemption

Hierarchical general register file (GRF) for execution block

Thread prefetch mechanism

Engine to enable high speed context switching via on-die storage

Hybrid low power homogenous grapics processing units

Apparatus and method for scalable error detection and reporting

Workload scheduling and distribution on a distributed graphics device

Coarse grain coherency

Apparatus and method for scalable error detection and reporting

Hybrid low power homogenous grapics processing units

Workload scheduling and distribution on a distributed graphics device

Coarse grain coherency

Apparatus and method for scalable error detection and reporting

Flexible partitioning of GPU resources

Multi-render partitioning

Accelerator controller hub

Scalable I/O virtualization interrupt and scheduling

KOKER ALTUG

Engine to enable high speed context switching via on-die storage

COORAY NIRANJAN L

Apparatus and method for memory management in a graphics processing environment

KABURLASOS NIKOS

Processor core with higher performance burst operation with lower power dissipation sustained workload mode