Inventor
BOROLE BHUSHAN M
US36 patents
Patents
36 patentsUS10444817B2Oct 15, 2019
System, apparatus and method for increasing performance in a processor during a voltage ramp
INTEL CORP8 citations84
US10430147B2Oct 1, 2019
Collaborative multi-user virtual reality
INTEL CORP9 citations84
US10102149B1Oct 16, 2018
Replacement policies for a hybrid hierarchical cache
INTEL CORP11 citations83
US11520555B2Dec 6, 2022
Collaborative multi-user virtual reality
INTEL CORP2 citations73
US11175719B2Nov 16, 2021
System, apparatus and method for increasing performance in a processor during a voltage ramp
INTEL CORP3 citations73
US11080810B2Aug 3, 2021
Dynamically reconfigurable memory subsystem for graphics processors
INTEL CORP2 citations73
US10579121B2Mar 3, 2020
Processor power management
INTEL CORP2 citations73
US10908865B2Feb 2, 2021
Collaborative multi-user virtual reality
INTEL CORP3 citations72
US10409319B2Sep 10, 2019
System, apparatus and method for providing a local clock signal for a memory array
INTEL CORP2 citations72
US10790010B2Sep 29, 2020
System, apparatus and method for segmenting a memory array
INTEL CORP1 citations71
US12124310B2Oct 22, 2024
Processor power management
INTEL CORP0 citations63
US11733758B2Aug 22, 2023
Processor power management
INTEL CORP0 citations63
US11106264B2Aug 31, 2021
Processor power management
INTEL CORP0 citations63
US10901909B2Jan 26, 2021
Optimizing read only memory surface accesses
INTEL CORP0 citations63
US12399546B2Aug 26, 2025
System, apparatus and method for increasing performance in a processor during a voltage ramp
INTEL CORP0 citations62
US12007824B2Jun 11, 2024
System, apparatus and method for increasing performance in a processor during a voltage ramp
INTEL CORP0 citations62
US11762696B2Sep 19, 2023
Hybrid low power homogenous grapics processing units
INTEL CORP0 citations62
US11263720B2Mar 1, 2022
Frequent data value compression for graphics processing units
INTEL CORP0 citations62
US11263152B2Mar 1, 2022
Replacement policies for a hybrid hierarchical cache
INTEL CORP0 citations62
US11169850B2Nov 9, 2021
Hybrid low power homogenous grapics processing units
INTEL CORP0 citations62
US10580104B2Mar 3, 2020
Read/write modes for reducing power consumption in graphics processing units
INTEL CORP1 citations62
US11176990B2Nov 16, 2021
System, apparatus and method for segmenting a memory array
INTEL CORP0 citations61
US10761591B2Sep 1, 2020
Shutting down GPU components in response to unchanged scene detection
INTEL CORP0 citations52
US10587244B2Mar 10, 2020
Pulse triggered flip flop
INTEL CORP0 citations52
US10521271B2Dec 31, 2019
Hybrid low power homogenous grapics processing units
INTEL CORP0 citations52
US10158346B2Dec 18, 2018
Pulse triggered flip flop
INTEL CORP0 citations52
US10817012B2Oct 27, 2020
System, apparatus and method for providing a local clock signal for a memory array
INTEL CORP0 citations51
US10748238B2Aug 18, 2020
Frequent data value compression for graphics processing units
INTEL CORP0 citations51
US10691617B2Jun 23, 2020
Replacement policies for a hybrid hierarchical cache
INTEL CORP0 citations51
US10319070B2Jun 11, 2019
Dynamic page sizing of page table entries
INTEL CORP0 citations51
US10262388B2Apr 16, 2019
Frequent data value compression for graphics processing units
INTEL CORP0 citations51
US10157444B2Dec 18, 2018
Dynamic page sizing of page table entries
INTEL CORP0 citations51
US10754809B2Aug 25, 2020
Reducing aging of register file keeper circuits
INTEL CORP0 citations50
US10347324B2Jul 9, 2019
System, apparatus and method for segmenting a memory array
INTEL CORP0 citations50
US10324721B2Jun 18, 2019
Reducing aging of register file keeper circuits
INTEL CORP0 citations50
US10762877B2Sep 1, 2020
System, apparatus and method for reducing voltage swing on an interconnect
INTEL CORP0 citations42