Inventor

ANDRIEU FRANCOIS

FR22 patents

⚠️ This page may combine multiple inventors who share the name “ANDRIEU FRANCOIS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ANDRIEU FRANCOIS

COMMISSARIAT ENERGIE ATOMIQUE

Method for manufacturing a substrate provided with different active areas and with planar and three-dimensional transistors

Integrated circuit comprising PMOS transistors with different voltage thresholds

Method for making a semiconductor structure with a buried ground plane

3D circuit provided with mesa isolation for the ground plane zone

Production of a 3D circuit with upper level transistor provided with a gate dielectric derived from a substrate transfer

Integrated circuit with NMOS and PMOS transistors having different threshold voltages through channel doping and gate material work function schemes

Fabrication of active areas of different natures directly onto an insulator: application to the single or double gate MOS transistor

Assembly for 3D circuit with superposed transistor levels

Method for stressing a thin pattern and transistor fabrication method incorporating said method

Method of fabricating a semiconductor substrate having a stressed semiconductor region

3D circuit transistors with flipped gate

3D SRAM circuit with double gate transistors with improved layout

Process for fabricating SOI transistors for an increased integration density

Integrated circuit comprising balanced cells at the active

Integrated circuit including balanced cells limiting an active area

Process for fabricating a transistor comprising nanoscale semiconductor features using block copolymers

ST MICROELECTRONICS CROLLES 2 SAS

Method of forming strained MOS transistors

Integrated circuit chip with strained NMOS and PMOS transistors

Integrated circuit chip with strained NMOS and PMOS transistors

Method of manufacturing a device with MOS transistors

THOMSON CSF

Combined microwave and optic rotary joint

LE TIEC YANNICK

Method for making a semiconductor structure with a buried ground plane