Inventor
BATRA POOJA R
US6 patents
Patents
6 patentsUS9870979B2Jan 16, 2018
Double-sided segmented line architecture in 3D integration
IBM10 citations81
US9559040B2Jan 31, 2017
Double-sided segmented line architecture in 3D integration
IBM14 citations81
US9543229B2Jan 10, 2017
Combination of TSV and back side wiring in 3D integration
IBM2 citations72
US9536809B2Jan 3, 2017
Combination of TSV and back side wiring in 3D integration
IBM3 citations72
US9263454B2Feb 16, 2016
Semiconductor structure having buried conductive elements
IBM0 citations52
US9245892B2Jan 26, 2016
Semiconductor structure having buried conductive elements
IBM0 citations52