Inventor

KODAMA CHIKAAKI

JP39 patents

⚠️ This page may combine multiple inventors who share the name “KODAMA CHIKAAKI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KODAMA CHIKAAKI

TOSHIBA KK

Semiconductor device

Layout correcting method, recording medium and design layout correcting apparatus

Mask pattern data creation method and mask

Method for manufacturing semiconductor device

Manufacturing method of a semiconductor device and method for creating a layout thereof

Manufacturing method of a semiconductor device and method for creating a layout thereof

Pattern generation method, computer-readable recording medium, and semiconductor device manufacturing method

Method of fabricating semiconductor device and semiconductor device

Method of manufacturing semiconductor device using sidewall films for pitch multiplication in forming interconnects

Production method and evaluation apparatus for mask layout

Microstructure device and method for manufacturing the same

Pattern data generation method, pattern verification method, and optical image calculation method

Pattern data generation method, pattern verification method, and optical image calculation method

Integrated circuit device, method for producing mask layout, and program for producing mask layout

TOSHIBA MEMORY CORP

Manufacturing method of a semiconductor device and method for creating a layout thereof

Manufacturing method of a semiconductor device and method for creating a layout thereof

Manufacturing method of a semiconductor device and method for creating a layout thereof

Assist pattern arrangement method and recording medium

Method of wiring layout, semiconductor device, program for supporting design of wiring layout, and method for manufacturing semiconductor device

Method of wiring layout, semiconductor device, program for supporting design of wiring layout, and method for manufacturing semiconductor device

Manufacturing method of a semiconductor device and method for creating a layout thereof

Semiconductor device having contacts in drawing area and the contacts connected to word lines extending from element formation area

KIOXIA CORP

Manufacturing method of a semiconductor device and method for creating a layout thereof

Manufacturing method of a semiconductor device and method for creating a layout thereof

Manufacturing method of a semiconductor device and method for creating a layout thereof

KODAMA CHIKAAKI

Sub-resolution assist feature arranging method and computer program product and manufacturing method of semiconductor device

Mask pattern generating method and computer program product

Mask pattern verification apparatus, mask pattern verification method and method of fabricating a semiconductor device

YANAGIDAIRA KOSUKE

Manufacturing method of a semiconductor device and method for creating a layout thereof

Manufacturing method of a semiconductor device and method for creating a layout thereof

TAGUCHI TAKAFUMI

Pattern dimension calculation method and computer program product

Pattern generating method, method of manufacturing semiconductor device, and recording medium

FUJITSU LTD

Wiring diagram verifying method, program, and apparatus

Wiring graphic verification method, program and apparatus

MASHITA HIROMITSU

Method for manufacturing semiconductor device and computer readable medium for storing pattern size setting program

Method of manufacturing semiconductor device and computer readable medium for storing pattern size setting program

KODERA KATSUYOSHI

Mask-layout creating method, apparatus therefor, and computer program product

ABURADA RYOTA

Method of fabricating semiconductor device and semiconductor device

NAKAMURA SATOMI

Original plate evaluation method, computer readable storage medium, and original plate manufacturing method