Inventor
LI SHIDONG
US60 patents
⚠️ This page may combine multiple inventors who share the name “LI SHIDONG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
42 patentsUS9089052B2Jul 21, 2015
Multichip module with stiffening frame and associated covers
IBM17 citations92
US11191155B1Nov 30, 2021
Tamper-respondent assembly with structural material within sealed inner compartment
IBM16 citations84
US10566313B1Feb 18, 2020
Integrated circuit chip carrier with in-plane thermal conductance layer
IBM8 citations84
US10056268B2Aug 21, 2018
Limiting electronic package warpage
IBM7 citations84
US9673064B2Jun 6, 2017
Interposer with lattice construction and embedded conductive metal structures
IBM4 citations84
US9666539B1May 30, 2017
Packaging for high speed chip to chip communication
IBM12 citations84
US9443799B2Sep 13, 2016
Interposer with lattice construction and embedded conductive metal structures
IBM9 citations84
US9089051B2Jul 21, 2015
Multichip module with stiffening frame and associated covers
IBM6 citations84
US11527462B2Dec 13, 2022
Circuit substrate with mixed pitch wiring
IBM3 citations73
US11302651B2Apr 12, 2022
Laminated stiffener to control the warpage of electronic chip carriers
IBM2 citations73
US10460956B2Oct 29, 2019
Interposer with lattice construction and embedded conductive metal structures
IBM1 citations73
US9953935B2Apr 24, 2018
Packaging for high speed chip to chip communication
IBM2 citations73
US9613915B2Apr 4, 2017
Reduced-warpage laminate structure
IBM2 citations73
US9543255B2Jan 10, 2017
Reduced-warpage laminate structure
IBM3 citations73
US10804181B2Oct 13, 2020
Heterogeneous thermal interface material for corner and or edge degradation mitigation
IBM2 citations72
US9093563B2Jul 28, 2015
Electronic module assembly with patterned adhesive array
IBM4 citations71
US11121096B2Sep 14, 2021
Active control of electronic package warpage
IBM0 citations63
US10593564B2Mar 17, 2020
Lid attach optimization to limit electronic package warpage
IBM1 citations63
US10083919B2Sep 25, 2018
Packaging for high speed chip to chip communication
IBM1 citations63
US10083886B2Sep 25, 2018
Lid attach optimization to limit electronic package warpage
IBM1 citations63
US11887908B2Jan 30, 2024
Electronic package structure with offset stacked chips and top and bottom side cooling lid
IBM0 citations62
US11784160B2Oct 10, 2023
Asymmetric die bonding
IBM0 citations62
US11410894B2Aug 9, 2022
Polygon integrated circuit (IC) packaging
IBM1 citations62
US10916507B2Feb 9, 2021
Multiple chip carrier for bridge assembly
IBM0 citations62
US10607928B1Mar 31, 2020
Reduction of laminate failure in integrated circuit (IC) device carrier
IBM1 citations62
US12052825B2Jul 30, 2024
Flexible circuit structure for circuit line bending
IBM0 citations61
US11569181B2Jan 31, 2023
Mitigating moisture-driven degradation of features designed to prevent structural failure of semiconductor wafers
IBM0 citations61
US10892233B2Jan 12, 2021
Mitigating moisture-driven degradation of features designed to prevent structural failure of semiconductor wafers
IBM0 citations61
US11756930B2Sep 12, 2023
High bandwidth module
IBM0 citations60
US11201136B2Dec 14, 2021
High bandwidth module
IBM0 citations60
US12581600B2Mar 17, 2026
Generation of random security circuit patterns for in-situ fabrication of tamper-respondent sensors
IBM0 citations59
US11430710B2Aug 30, 2022
Lid/heat spreader having targeted flexibility
IBM0 citations59
US11694992B2Jul 4, 2023
Near tier decoupling capacitors
IBM0 citations57
US12431404B2Sep 30, 2025
Fatigue failure resistant electronic package
IBM0 citations52
US10685919B2Jun 16, 2020
Reduced-warpage laminate structure
IBM0 citations52
US10636746B2Apr 28, 2020
Method of forming an electronic package
IBM0 citations52
US10332813B2Jun 25, 2019
Lid attach optimization to limit electronic package warpage
IBM0 citations52
US10049896B2Aug 14, 2018
Lid attach optimization to limit electronic package warpage
IBM1 citations52
US9947603B2Apr 17, 2018
Lid attach optimization to limit electronic package warpage
IBM0 citations52
US9892935B2Feb 13, 2018
Limiting electronic package warpage with semiconductor chip lid and lid-ring
IBM1 citations52
US8940550B1Jan 27, 2015
Maintaining laminate flatness using magnetic retention during chip joining
IBM1 citations52
US9818682B2Nov 14, 2017
Laminate substrates having radial cut metallic planes
IBM1 citations51
GLOBALFOUNDRIES INC
2 patentsQingdao haier refrigerator co ltd
2 patentsHAIER SMART HOME CO LTD
1 patent(unassigned)
1 patentLI SHIDONG
1 patentUNIV GUILIN TECHNOLOGY
1 patentShowing the top 50 of 60 patents by PatentIndex Score.