Inventor
AGARWALA BIRENDRA N
US16 patents
Patents
16 patentsUS6033939AMar 7, 2000
Method for providing electrically fusible links in copper interconnection
IBM152 citations98
US5376584ADec 27, 1994
Process of making pad structure for solder ball limiting metallurgy having reduced edge stress
IBM163 citations98
US5251806AOct 12, 1993
Method of forming dual height solder interconnections
IBM144 citations98
US5130779AJul 14, 1992
Solder mass having conductive encapsulating arrangement
IBM185 citations98
US6734090B2May 11, 2004
Method of making an edge seal for a semiconductor device
IBM605 citations97
US5268072ADec 7, 1993
Etching processes for avoiding edge stress in semiconductor chip solder bumps
IBM119 citations96
US7279411B2Oct 9, 2007
Process for forming a redundant structure
IBM23 citations92
US7224063B2May 29, 2007
Dual-damascene metallization interconnection
IBM30 citations92
US4985310AJan 15, 1991
Multilayered metallurgical structure for an electronic component
IBM51 citations92
US4970570ANov 13, 1990
Use of tapered head pin design to improve the stress distribution in the braze joint
IBM34 citations92
US7163883B2Jan 16, 2007
Edge seal for a semiconductor device
IBM27 citations91
US6972209B2Dec 6, 2005
Stacked via-stud with improved reliability in copper metallurgy
IBM32 citations90
US6825561B1Nov 30, 2004
Structure and method for eliminating time dependent dielectric breakdown failure of low-k material
IBM15 citations84
US6271599B1Aug 7, 2001
Wire interconnect structure for electrically and mechanically connecting an integrated circuit chip to a substrate
IBM16 citations84
US7470613B2Dec 30, 2008
Dual damascene multi-level metallization
IBM7 citations73
US7138714B2Nov 21, 2006
Via barrier layers continuous with metal line barrier layers at notched or dielectric mesa portions in metal lines
IBM10 citations73