Inventor
HUANG CHENDER
US29 patents
⚠️ This page may combine multiple inventors who share the name “HUANG CHENDER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TAIWAN SEMICONDUCTOR MFG
21 patentsUS6770958B2Aug 3, 2004
Under bump metallization structure
TAIWAN SEMICONDUCTOR MFG80 citations98
US6656827B1Dec 2, 2003
Electrical performance enhanced wafer level chip scale package with ground
TAIWAN SEMICONDUCTOR MFG142 citations98
US6939789B2Sep 6, 2005
Method of wafer level chip scale packaging
TAIWAN SEMICONDUCTOR MFG84 citations97
US6596619B1Jul 22, 2003
Method for fabricating an under bump metallization structure
TAIWAN SEMICONDUCTOR MFG48 citations96
US6528417B1Mar 4, 2003
Metal patterned structure for SiN surface adhesion enhancement
TAIWAN SEMICONDUCTOR MFG24 citations93
US7294937B2Nov 13, 2007
Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling
TAIWAN SEMICONDUCTOR MFG26 citations92
US7126225B2Oct 24, 2006
Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling
TAIWAN SEMICONDUCTOR MFG29 citations92
US7026711B2Apr 11, 2006
Thermal dispensing enhancement for high performance flip chip BGA (HPFCBGA)
TAIWAN SEMICONDUCTOR MFG33 citations92
US6782897B2Aug 31, 2004
Method of protecting a passivation layer during solder bump formation
TAIWAN SEMICONDUCTOR MFG52 citations92
US6372619B1Apr 16, 2002
Method for fabricating wafer level chip scale package with discrete package encapsulation
TAIWAN SEMICONDUCTOR MFG64 citations92
US7157734B2Jan 2, 2007
Semiconductor bond pad structures and methods of manufacturing thereof
TAIWAN SEMICONDUCTOR MFG23 citations87
US7015066B2Mar 21, 2006
Method for stress reduction in flip chip bump during flip chip mounting and underfill process steps of making a microelectronic assembly
TAIWAN SEMICONDUCTOR MFG11 citations84
US6774026B1Aug 10, 2004
Structure and method for low-stress concentration solder bumps
TAIWAN SEMICONDUCTOR MFG14 citations84
US6960518B1Nov 1, 2005
Buildup substrate pad pre-solder bump manufacturing
TAIWAN SEMICONDUCTOR MFG12 citations83
US7190066B2Mar 13, 2007
Heat spreader and package structure utilizing the same
TAIWAN SEMICONDUCTOR MFG14 citations82
US6638837B1Oct 28, 2003
Method for protecting the front side of semiconductor wafers
TAIWAN SEMICONDUCTOR MFG12 citations73
US7638887B2Dec 29, 2009
Package structure and fabrication method thereof
TAIWAN SEMICONDUCTOR MFG3 citations63
US7443010B2Oct 28, 2008
Matrix form semiconductor package substrate having an electrode of serpentine shape
TAIWAN SEMICONDUCTOR MFG6 citations63
US6884662B1Apr 26, 2005
Enhanced adhesion strength between mold resin and polyimide
TAIWAN SEMICONDUCTOR MFG2 citations62
US7390697B2Jun 24, 2008
Enhanced adhesion strength between mold resin and polyimide
TAIWAN SEMICONDUCTOR MFG0 citations51
US7378731B2May 27, 2008
Heat spreader and package structure utilizing the same
TAIWAN SEMICONDUCTOR MFG0 citations50
MICRON TECHNOLOGY INC
5 patentsUS5214845AJun 1, 1993
Method for producing high speed integrated circuits
MICRON TECHNOLOGY INC407 citations99
US5302891AApr 12, 1994
Discrete die burn-in for non-packaged die
MICRON TECHNOLOGY INC224 citations98
US5150194ASep 22, 1992
Anti-bow zip lead frame design
MICRON TECHNOLOGY INC62 citations96
US6091250AJul 18, 2000
Discrete die burn-in for nonpackaged die
MICRON TECHNOLOGY INC33 citations92
US6998860B1Feb 14, 2006
Method for burn-in testing semiconductor dice
MICRON TECHNOLOGY INC4 citations62