Inventor

VASSILIADIS STAMATIS

US75 patents

⚠️ This page may combine multiple inventors who share the name “VASSILIADIS STAMATIS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

VASSILIADIS STAMATIS

IBM

Improved method to prefetch load instruction data

In-memory preprocessor for compounding a sequence of instructions for parallel computer system execution

Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit

Generalized 7/3 counters

Dynamic multiple instruction stream multiple data multiple pipeline apparatus for floating-point single instruction stream single data architectures

Method of indicating parallel execution compoundability of scalar instructions based on analysis of presumed instructions

Multi-function permutation switch for rotating and manipulating an order of bits of an input data byte in either cyclic or non-cyclic mode

Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism

Massively parallel array processor

Parallel processing system and method using surrogate instructions

Learning machine synapse processor system apparatus

System for obtaining parallel execution of existing instructions in a particulr data processing configuration by compounding rules based on instruction categories

Status predictor for combined shifter-rotate/merge unit

Learning machine synapse processor system apparatus

Triangular scalable neural array processor

System for executing scalar instructions in parallel based on control bits appended by compounding decoder

System and method for obtaining parallel existing instructions in a particular data processing configuration by compounding instructions

Predecode instruction compounding

System for comounding instructions in a byte stream prior to fetching and identifying the instructions for execution

Apparatus for initializing branch prediction information

SPIN: a sequential pipeline neurocomputer

Pyramid learning architecture neurocomputer

System for issuing instructions for parallel execution subsequent to branch into a group of member instructions with compoundability in dictation tag

Compounding preprocessor for cache for identifying multiple instructions which may be executed in parallel

Memory management for scalable compound instruction set machines with in-memory compounding

Scalable neural array processor

Data dependency collapsing hardware apparatus

Massively parallel diagonal-fold tree array processor

Clustering fuzzy expected value system

Fuzzy reasoning database question answering system

Method for processing instructions for parallel execution including storing instruction sequences along with compounding information in cache

Processor using folded array structures for transposition memory and fast cosine transform computation

Cache store of instruction pairs with tags to indicate parallel execution

Compounding preprocessor for cache for identifying multiple instructions which may be executed in parallel

Scalable neural array processor and method

Communicating adder tree system for neural array processor

Massively parallel multiple-folded clustered processor mesh array

Scalable parallel group partitioned diagonal-fold switching tree computing apparatus

Processing element for parallel array processor

Data dependency collapsing hardware apparatus

Apparatus for predicting overlapped storage operands for move character

Address prediction to avoid address generation interlocks in computer systems

3-1 Arithmetic logic unit for simultaneous execution of an independent or dependent add/logic instruction pair

Scalable flow virtual learning neurocomputer

Overflow determination for three-operand alus in a scalable compound instruction set machine which compounds two arithmetic instructions

High performance interlock collapsing SCISM ALU apparatus

Virtual neurocomputer architectures for neural networks

Method and apparatus for modified carry-save determination of arithmetic/logic zero results

LUCENT TECHNOLOGIES INC

Compiler-controlled dynamic instruction dispatch in pipelined processors

Multiple machine view execution in a computer system