Inventor

WEBB CHARLES F

US62 patents

⚠️ This page may combine multiple inventors who share the name “WEBB CHARLES F”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WEBB CHARLES F

IBM

System for transferring data between I/O devices and main or expanded storage under dynamic control of independent indirect address words (IDAWs)

Data processor with enhanced error recovery

Checkpoint synchronization with instruction overlap enabled

Method, system and computer program product for providing filtering of GUEST2 quiesce requests

Program store compare handling between instruction and operand caches

Method of using small addresses to access any guest zone in a large memory

Subroutine return through branch history table

System for monitoring and undoing execution of instructions beyond a serialization point upon occurrence of in-correct results

Method for processing checkpoint instructions to allow concurrent execution of overlapping instructions

System and method for modifying program status word system mask, system access key, and address space code with overlap enabled

Method and system for managing the result from a translator co-processor in a pipelined processor

Operand fetching control as a function of branch confidence

Dynamic address translation with format control

System and method for avoiding deadlocks when performing storage updates in a multi-processor environment

Specialized millicode instruction for range checking

Multiprocessor system with a shared control store accessed with predicted addresses

Dynamic address translation with fetch protection in an emulated environment

Dynamic address translation with translation table entry format control for identifying format of the translation table entry

Specialized millicode instruction for string operations

Read only store as part of cache store for storing frequently used millicode instructions

Dynamic address translation with access control in an emulator environment

Memory state indicator check operations

Memory state indicator check operations

Load pair disjoint facility and instruction therefor

Shared memory translation facility

System, method and computer program product for handling shared cache lines in a multi-processor environment

Method, system and program products for generating sequence values that are unique across operating system images

Method and system for testing millicode branch points

Managing instruction execution in order to accommodate a physical clock value in a clock representation

Directly initiating by external adapters the setting of interruption initiatives

Method of implementing a translation lookaside buffer with support for a real space control

Operational context subspaces

Method, system and computer program product for an implicit predicted return from a predicted subroutine

Write before read interlock for recovery unit operands

Memory state indicator

Memory state indicator

GREINER DAN F

Dynamic address translation with change record override

Dynamic address translation with translation table entry format control for indentifying format of the translation table entry

Dynamic address translation with change record override

Dynamic address translation with translation table entry format control for identifying format of the translation table entry

WEBB CHARLES F

Carpet cleaning machine

Carpet cleaning apparatus

Carpet cleaning apparatus

ALEXANDER KHARY J

Facilitating processing in a computing environment using an extended drain instruction

Facilitating processing in a computing environment using an extended drain instruction

JACOBI CHRISTIAN

Load pair disjoint facility and instruction therefore

EMMA PHILIP G

Branch prediction instructions having mask values involving unloading and loading branch history data

INTERNAT BUISNESS MACHINES CORP

Dynamic address translation with DAT protection

SCHROTER DAVID A

Microprocessor, method and computer program product for direct page prefetch in millicode capable computer system

HSIEH JONATHAN T

Processor, method and computer program product for fast selective invalidation of translation lookaside buffer