P

Inventor

TANG CHENG-LONG

US13 patents

Patents

13 patents
US6611908B2Aug 26, 2003

Microprocessor architecture capable of supporting multiple heterogeneous processors

SEIKO EPSON CORP83 citations99
US6272579B1Aug 7, 2001

Microprocessor architecture capable of supporting multiple heterogeneous processors

SEIKO EPSON CORP120 citations99
US5440752AAug 8, 1995

Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU

SEIKO EPSON CORP170 citations99
US5754800AMay 19, 1998

Multi processor system having dynamic priority based on row match of previously serviced address, number of times denied service and number of times serviced without interruption

SEIKO EPSON CORP86 citations97
US6954844B2Oct 11, 2005

Microprocessor architecture capable of supporting multiple heterogeneous processors

SEIKO EPSON CORP29 citations96
US6219763B1Apr 17, 2001

System and method for adjusting priorities associated with multiple devices seeking access to a memory array unit

SEIKO EPSON CORP55 citations96
US5941979AAug 24, 1999

Microprocessor architecture with a switch network and an arbitration unit for controlling access to memory ports

SEIKO EPSON CORP40 citations96
US5604865AFeb 18, 1997

Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU

SEIKO EPSON CORP50 citations96
US7657712B2Feb 2, 2010

Microprocessor architecture capable of supporting multiple heterogeneous processors

SEIKO EPSON CORP10 citations93
US6047348AApr 4, 2000

System and method for supporting a multiple width memory subsystem

SEIKO EPSON CORP37 citations92
US5594877AJan 14, 1997

System for transferring data onto buses having different widths

SEIKO EPSON CORP25 citations92
US5887148AMar 23, 1999

System for supporting a buffer memory wherein data is stored in multiple data widths based upon a switch interface for detecting the different bus sizes

SEIKO EPSON CORP11 citations74
US5828861AOct 27, 1998

System and method for reducing the critical path in memory control unit and input/output control unit operations

SEIKO EPSON CORP3 citations63