Inventor
CHEN HONG-YI
US39 patents
⚠️ This page may combine multiple inventors who share the name “CHEN HONG-YI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
MARVELL INT LTD
10 patentsUS7558942B1Jul 7, 2009
Memory mapped register file and method for accessing the same
MARVELL INT LTD178 citations97
US7437532B1Oct 14, 2008
Memory mapped register file
MARVELL INT LTD24 citations91
US8347034B1Jan 1, 2013
Transparent level 2 cache that uses independent tag and valid random access memory arrays for cache access
MARVELL INT LTD12 citations82
US7685372B1Mar 23, 2010
Transparent level 2 cache controller
MARVELL INT LTD8 citations82
US7568083B1Jul 28, 2009
Memory mapped register file and method for accessing the same
MARVELL INT LTD8 citations82
US8935591B1Jan 13, 2015
System and method to correct errors in data read from a source supplying streaming data
MARVELL INT LTD1 citations63
US7949833B1May 24, 2011
Transparent level 2 cache controller
MARVELL INT LTD2 citations61
US7730285B1Jun 1, 2010
Data processing system with partial bypass reorder buffer and combined load/store arithmetic logic unit and processing method thereof
MARVELL INT LTD4 citations61
US8621152B1Dec 31, 2013
Transparent level 2 cache that uses independent tag and valid random access memory arrays for cache access
MARVELL INT LTD2 citations59
US8667370B1Mar 4, 2014
Systems and methods for arbitrating use of processor memory
MARVELL INT LTD0 citations52
MARVELL WORLD TRADE LTD
7 patentsUS7730335B2Jun 1, 2010
Low power computer with main and auxiliary processors
MARVELL WORLD TRADE LTD11 citations93
US7788514B2Aug 31, 2010
Low power computer with main and auxiliary processors
MARVELL WORLD TRADE LTD7 citations74
US7827423B2Nov 2, 2010
Low power computer with main and auxiliary processors
MARVELL WORLD TRADE LTD3 citations63
US8526257B2Sep 3, 2013
Processor with memory delayed bit line precharging
MARVELL WORLD TRADE LTD2 citations61
US8027218B2Sep 27, 2011
Processor instruction cache with dual-read modes
MARVELL WORLD TRADE LTD3 citations61
US8874948B2Oct 28, 2014
Apparatuses for operating, during respective power modes, transistors of multiple processors at corresponding duty cycles
MARVELL WORLD TRADE LTD0 citations52
US7787324B2Aug 31, 2010
Processor instruction cache with dual-read modes
MARVELL WORLD TRADE LTD0 citations51
CHEN HONG-YI
5 patentsUS8195922B2Jun 5, 2012
System for dynamically allocating processing time to multiple threads
CHEN HONG-YI52 citations97
US8074056B1Dec 6, 2011
Variable length pipeline processor architecture
CHEN HONG-YI13 citations82
US8468324B2Jun 18, 2013
Dual thread processor
CHEN HONG-YI4 citations62
US8909903B1Dec 9, 2014
Providing data to registers between execution stages
CHEN HONG-YI0 citations50
US8078828B1Dec 13, 2011
Memory mapped register file
CHEN HONG-YI0 citations50
SUTARDJA SEHAT
4 patentsUS8572416B2Oct 29, 2013
Low power computer with main and auxiliary processors
SUTARDJA SEHAT8 citations84
US9158355B2Oct 13, 2015
Dynamic core switching
SUTARDJA SEHAT6 citations73
US8295110B2Oct 23, 2012
Processor instruction cache with dual-read modes
SUTARDJA SEHAT2 citations61
US8089823B2Jan 3, 2012
Processor instruction cache with dual-read modes
SUTARDJA SEHAT0 citations51
UNITED MICROELECTRONICS CORP
3 patentsUS5828590AOct 27, 1998
Multiplier based on a variable radix multiplier coding
UNITED MICROELECTRONICS CORP25 citations89
US5793659AAug 11, 1998
Method of modular reduction and modular reduction circuit
UNITED MICROELECTRONICS CORP28 citations89
US5864372AJan 26, 1999
Apparatus for implementing a block matching algorithm for motion estimation in video image processing
UNITED MICROELECTRONICS CORP21 citations86