Inventor

HENRY G GLENN

US379 patents

⚠️ This page may combine multiple inventors who share the name “HENRY G GLENN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HENRY G GLENN

IP FIRST LLC

Translation lookaside buffer that caches memory type information

Compare branch instruction pairing within a single integer pipeline

Static branch prediction mechanism for conditional branch instructions

Method and apparatus for speculatively forwarding storehit data in a hierarchical manner

Speculative hybrid branch direction predictor

Apparatus for performing branch target address calculation based on branch type

Hybrid branch predictor with improved selector table update mechanism

Apparatus and method for speculatively updating global history and restoring same on branch misprediction detection

Apparatus and method for branch target address calculation during instruction decode

Microprocessor apparatus and method for performing block cipher cryptographic functions

Apparatus and method for extending a microprocessor instruction set

Mechanism for extending the number of registers in a microprocessor

Microprocessor apparatus and method for performing block cipher cryptographic functions

Apparatus and method for selective memory attribute control

Apparatus and method for extending a microprocessor instruction set

Random number generator with selectable dual random bit string engines

Random number generator bit string filter

Microprocessor and method for utilizing disparity between bus clock and core clock frequencies to prioritize cache line fill bus access requests

Pop-compare micro instruction for repeat string operations

Continuous multi-buffering random number generator

Microprocessor and method for performing selective prefetch based on bus activity level

Virtual set cache that redirects store data to correct virtual set to avoid virtual set store miss penalty

Apparatus and method for speculatively forwarding storehit data based on physical page index compare

Result forwarding cache

Pairing of micro instructions in the instruction queue

Method and apparatus for performing branch prediction combining static and dynamic branch predictors

Apparatus and method for fast forward branch

Microprocessor having fuse control and selection of clock multiplier

Apparatus and method for executing a single-cycle exchange instruction to exchange contents of two locations in a register file

Method and apparatus for improved aligned/misaligned data load from cache

VIA TECH INC

Microprocessor mechanism for decompression of fuse correction data

Initialization of a microprocessor providing for execution of secure code

Processor that performs approximate computing instructions

Apparatus and method for compression and decompression of microprocessor configuration data

Apparatus and method for secure hash algorithm

Microprocessor apparatus providing for secure interrupts and exceptions

Apparatus and method for instruction-level specification of floating point format

Microprocessor apparatus and method for providing configurable cryptographic block cipher round results

VIA ALLIANCE SEMICONDUCTOR CO LTD

Processor with memory array operable as either last level cache slice or neural network unit memory

Neural network unit with memory layout to perform efficient 3-dimensional convolutions

Neural network unit that performs efficient 3-dimensional convolutions

Neural network unit with shared activation function units

Multi-operation neural network unit

Neural network unit that performs stochastic rounding

HENRY G GLENN

Apparatus and method for managing a microprocessor providing for a secure execution mode

Accessing model specific registers (MSR) with different sets of distinct microinstructions for instructions of different instruction set architecture (ISA)

Termination of secure execution mode in a microprocessor providing for execution of secure code

Microprocessor having secure non-volatile storage access

INTEGRATED DEVICE TECH

Fuse array control for smart function enable

Apparatus and method for exception handling during micro code string instructions