Inventor

GASKINS STEPHAN

US32 patents

⚠️ This page may combine multiple inventors who share the name “GASKINS STEPHAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GASKINS STEPHAN

VIA TECH INC

Selective designation of multiple cores as bootstrap processor in a multi-core microprocessor

Inter-core communication via uncore RAM

Propagation of updates to per-core-instantiated architecturally-visible storage resource

Multi-core microprocessor that dynamically designates one of its processing cores as the bootstrap processor

Single core wakeup multi-core synchronization mechanism

Microprocessor capable of dynamically reducing its power consumption in response to varying operating temperature

Propagation of microcode patches to multiple cores in multicore microprocessor

Core ID designation system for dynamically designated bootstrap processor

Service processor patch mechanism

Reconfigurably designating master core for conditional output on sideband communication wires distinct from system bus

Microprocessor capable of dynamically increasing its performance in response to varying operating temperature

Method and apparatus for waking a single core of a multi-core microprocessor, while maintaining most cores in a sleep state

Propagation of updates to per-core-instantiated architecturally-visible storage resource

Multi-core data array power gating restoral mechanism

Dynamic cache enlarging by counting evictions

VIA ALLIANCE SEMICONDUCTOR CO LTD

Cache memory diagnostic writeback

Multi-core data array power gating restoral mechanism

Apparatus and method for repairing cache arrays in a multi-core microprocessor

Multi-core programming apparatus and method for restoring data arrays following a power gating event

Multi-core apparatus and method for restoring data arrays following a power gating event

Multi-core microprocessor power gating cache restoral programming mechanism

Multi-core programming apparatus and method for restoring data arrays following a power gating event

Multi-core data array power gating cache restoral programming mechanism

Multi-core microprocessor power gating cache restoral mechanism

HENRY G GLENN

Multi-core processor with core selectively disabled by kill instruction of system software and resettable only via external pin

Multicore processor power credit management to allow all processing cores to operate at elevated frequency

Detection of uncorrectable re-grown fuses in a microprocessor

Microprocessor with multicore processor power credit management feature

Multicore processor power credit management in which multiple processing cores use shared memory to communicate individual energy consumption

GASKINS DARIUS D

Microprocessor that performs adaptive power throttling

Detection of fuse re-growth in a microprocessor

Microprocessor that performs adaptive power throttling