Inventor

THURBER STEVEN MARK

US72 patents

⚠️ This page may combine multiple inventors who share the name “THURBER STEVEN MARK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

THURBER STEVEN MARK

IBM

System, method, and product in a logically partitioned system for prohibiting I/O adapters from accessing memory assigned to other partitions during DMA

Error recovery by isolation of peripheral components in a data processing system

Method and apparatus for reporting unauthorized attempts to access nodes in a network computing system

End node partitioning using LMC for a system area network

System area network of end-to-end context via reliable datagram domains

DMA windowing in an LPAR environment using device arbitration level to allow multiple IOAs per terminal bridge

Method and system for reliably defining and determining timeout values in unreliable datagrams

DMA access authorization for 64-bit I/O adapters on PCI bus

Computer system error recovery and fault isolation

System for determining whether a subsequent transaction may be allowed or must be allowed or must not be allowed to bypass a preceding transaction

Method and system for translating peripheral component interconnect (PCI) peer-to-peer access across multiple PCI host bridges within a computer system

Method and system for supporting peripheral component interconnect (PCI) peer-to-peer access across multiple PCI host bridges within a data-processing system

Method and apparatus for ensuring scalable mastership during initialization of a system area network

Method and apparatus for reliably choosing a master network manager during initialization of a network computing system

Autonomic recovery from hardware errors in an input/output fabric

Isolation of I/O bus errors to a single partition in an LPAR environment

Selectively flushing buffered transactions in a bus bridge

Method and system for supporting multiple local buses operating at different frequencies

Bus for high frequency operation with backward compatibility and hot-plug ability

Method and system for supporting peripheral component interconnect (PCI) peer-to-peer access across a PCI host bridge supporting multiple PCI buses

Autonomic recovery from hardware errors in an input/output fabric

Variable slot configuration for multi-speed bus

Scalable system interrupt structure for a multi-processing system

Method and apparatus for dynamic retention of system area network management information in non-volatile store

Method and system for informing an operating system in a system area network when a new device is connected

Method and system for choosing a queue protection key that is tamper-proof from an application

DMA windowing in an LPAR environment using device arbitration level to allow multiple IOAs per terminal bridge

Enhanced bus arbiter utilizing variable priority and fairness

Transaction routing system

Coherency for DMA read cached data

Device arbitration including peer-to-peer access arbitration

Method and system for interrupt handling using system pipelined packet transfers

System for determining whether a subsequent transaction may be allowed or must be allowed or must not be allowed to bypass a preceding transaction

Method and system for injecting errors to a device within a computer system

Method/system for identifying delayed predetermined information transfer request as bypassable by subsequently-generated information transfer request using bypass enable bit in bridge translation control entry

Dual host bridge with peer to peer support

Method and system for supporting multiple peripheral component interconnect PCI buses by a single PCI host bridge within a computer system

PCI system and adapter requirements following reset

Enhanced dual speed bus computer system

System and method for enhancement of system bus to mezzanine bus transactions

Isolation of input/output adapter error domains

Associating buffers in a bus bridge with corresponding peripheral devices to facilitate transaction merging

Interrupt response in a multiple set buffer pool bus bridge

Enhanced error handling for I/O load/store operations to a PCI device via bad parity or zero byte enables

Read request performance of a multiple set buffer pool bus bridge

Intelligent PCI/PCI-X host bridge

Method and apparatus for restricting input/output device peer-to-peer operations in a data processing system to improve reliability, availability, and serviceability

PCI/PCI-X bus bridge with performance monitor

Information routing for transfer buffers

BENDER CARL ALFRED

Stalling of DMA operations in order to do memory migration using a migration in progress bit in the translation control entry mechanism