Inventor

OLSSON BRETT

US70 patents

⚠️ This page may combine multiple inventors who share the name “OLSSON BRETT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

OLSSON BRETT

IBM

Fine-grained instruction enablement at sub-function granularity based on an indicated subrange of registers

Multi-addressable register file

Method and system in a data processing system for loading and storing vectors in a plurality of modes

Method and system for dynamically reconfiguring a register file in a vector processor

Numerically intensive computer accelerator

Method and system for providing a single-instruction, multiple-data execution unit for performing single-instruction, multiple-data operations within a superscalar data processing system

Implementing instruction set architectures with non-contiguous register file specifiers

Method and system for a result code for a single-instruction multiple-data predicate compare operation

Method and system for vector processing utilizing selected vector elements

Method and system for addressing registers in a data processing unit in an indirect addressing mode

Implementing instruction set architectures with non-contiguous register file specifiers

Method and apparatus for performing vector operation using separate multiplication on odd and even data elements of source vectors

Wide shifting in the vector permute unit

Wide shifting in the vector permute unit

Floating point instruction with selectable comparison attributes

Simultaneously capturing status information for multiple operating modes

Computer instructions for limiting access violation reporting when accessing strings and similar data structures

Multi-addressable register files and format conversions associated therewith

Sharing data in internal and memory representations with dynamic data-driven conversion

Apparatus and method for using branch prediction heuristics for determination of trace formation readiness

Apparatus and method for supporting simultaneous storage of trace and standard cache lines

Method and system for bounds comparator

Instructions to count contiguous register elements having a specific value in a selected location

Instructions to count contiguous register elements having a specific value in a selected location

Simultaneously capturing status information for multiple operating modes

Processing page fault exceptions in supervisory software when accessing strings and similar data structures using normal load instructions

Computer instructions for limiting access violation reporting when accessing strings and similar data structures

Reducing the fetch time of target instructions of a predicted taken branch instruction

Method and system for addressing registers in a data processing unit in an indexed addressing mode

Compute array of a processor with mixed-precision numerical linear algebra support

Compute array of a processor with mixed-precision numerical linear algebra support

Simultaneously capturing status information for multiple operating modes

Exception preserving parallel data processing of string and unstructured text

Simultaneously capturing status information for multiple operating modes

Instructions to count a number of contiguous register elements having specific values in a selected location

Instructions to count a number of contiguous register elements having specific values in a selected location

Structure for supporting simultaneous storage of trace and standard cache lines

Apparatus and method for using branch prediction heuristics for determination of trace formation readiness

Apparatus and method for saving power in a trace cache

Reducing the fetch time of target instructions of a predicted taken branch instruction

Three-dimensional lane predication for matrix operations

GSCHWIND MICHAEL KARL

Implementing instruction set architectures with non-contiguous register file specifiers

Implementing instruction set architectures with non-contiguous register file specifiers

Methods for generating code for an architecture encoding an extended register specification

Methods for generating code for an architecture encoding an extended register specification

Methods for generating code for an architecture encoding an extended register specification

MOTOROLA INC

Method and apparatus for generating an alignment control vector

Data processing system for processing vector data and method therefor

APPLE

Data processing system and method of permutation with replication within a vector register file

EICHENBERGER ALEXANDRE E

Method and structure of using SIMD vector architectures to implement matrix multiplication