Inventor

TSUCHIDA KENJI

JP85 patents

⚠️ This page may combine multiple inventors who share the name “TSUCHIDA KENJI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TSUCHIDA KENJI

TOSHIBA KK

Magnetic random access memory and reading method thereof

High-speed random access semiconductor memory device

High-speed cycle clock-synchronous memory device

Semiconductor memory capable of successively accessing cell array blocks with a plurality of operation modes having different cycle times

Dynamic semiconductor memory device with high-speed serial-accessing column decoder

MOS type random access memory with interference noise eliminator

Semiconductor memory device with variable resistance element

Resistance-change memory

Semiconductor memory

Magnetic random access memory having test circuit and test method therefor

Clock signal generator circuit and semiconductor integrated circuit with the same circuit

Semiconductor memory system, and access control method for semiconductor memory and semiconductor memory

Fuse programming circuit for programming fuses

Dynamic type RAM

Dynamic semiconductor memory device having an improved sense amplifier layout arrangement

Semiconductor memory device

Semiconductor memory device

Semiconductor memory device with column gate and equalizer circuitry

Constant-voltage generating device

Dynamic semiconductor memory device having an improved sense amplifier layout arrangement

Dynamic semiconductor memory device having a precharge circuit using low power consumption

Semiconductor memory device

MOS random access memory device with an internal voltage-down converting transistor

Dynamic random access memory with enhanced sense-amplifier circuit

Dynamic semiconductor memory device with twisted bit-line structure

Dynamic type semiconductor memory device

Magnetic random access memory

Semiconductor memory

MRAM having memory cell array in which cross-point memory cells are arranged by hierarchical bit line scheme and data read method thereof

Semiconductor memory device having overdriven bit-line sense amplifiers

Semiconductor device

Semiconductor memory device having segment type word line structure

Magnetic memory

Spin injection write type magnetic memory device

Read circuit of semiconductor and read method using a self-reference sensing technique

Semiconductor integrated circuit device

Semiconductor memory device with reduced its chip area and power consumption

Semiconductor memory device

Pump circuit boosting a supply voltage

Dynamic random access memory having continuous data line equalization except at address translation during data reading

Pump circuit boosting a supply voltage

Semiconductor memory device having a multilayered bitline structure with respective wiring layers for reading and writing data

Dynamic semiconductor memory device having an improved sense amplifier layout arrangement

Magnetic random access memory

Magnetoresistive random access memory and driving method thereof

MRAM having current peak suppressing circuit

TSUCHIDA KENJI

Resistance change memory

Resistance change memory

HOYA KATSUHIKO

Semiconductor storage device

SHIRAI YUTAKA

Nonvolatile random access memory including control circuit configured to receive commands at high and low edges of one clock cycle