Inventor

GAUTHIER CLAUDE R

US80 patents

Patents

50 patents

US6377076B1Apr 23, 2002

Circuitry to support a power/area efficient method for high-frequency pre-emphasis for chip to chip signaling

SUN MICROSYSTEMS INC82 citations98

US6265920B1Jul 24, 2001

Power/area efficient method for high-frequency pre-emphasis for intra-chip signaling

SUN MICROSYSTEMS INC22 citations93

US7129800B2Oct 31, 2006

Compensation technique to mitigate aging effects in integrated circuit components

SUN MICROSYSTEMS INC43 citations92

US6934652B2Aug 23, 2005

Negative bias temperature instability correction technique for delay locked loop and phase locked loop bias generators

SUN MICROSYSTEMS INC39 citations92

US6791360B2Sep 14, 2004

Source synchronous interface using variable digital data delay lines

SUN MICROSYSTEMS INC32 citations92

US6781355B2Aug 24, 2004

I/O power supply resonance compensation technique

SUN MICROSYSTEMS INC26 citations92

US6686785B2Feb 3, 2004

Deskewing global clock skew using localized DLLs

SUN MICROSYSTEMS INC37 citations92

US6570423B1May 27, 2003

Programmable current source adjustment of leakage current for phase locked loop

SUN MICROSYSTEMS INC22 citations92

US6476663B1Nov 5, 2002

Method for reducing supply noise near an on-die thermal sensor

SUN MICROSYSTEMS INC22 citations92

US6996491B2Feb 7, 2006

Method and system for monitoring and profiling an integrated circuit die temperature

SUN MICROSYSTEMS INC38 citations91

US6937958B2Aug 30, 2005

Controller for monitoring temperature

SUN MICROSYSTEMS INC22 citations91

US6774653B2Aug 10, 2004

Two-pin thermal sensor calibration interface

SUN MICROSYSTEMS INC32 citations91

US7109767B1Sep 19, 2006

Generating different delay ratios for a strobe delay

SUN MICROSYSTEMS INC20 citations90

US7283070B1Oct 16, 2007

Dynamic calibration of I/O power supply level

SUN MICROSYSTEMS INC11 citations84

US7251305B2Jul 31, 2007

Method and apparatus to store delay locked loop biasing parameters

SUN MICROSYSTEMS INC19 citations84

US7123995B1Oct 17, 2006

Dynamic circuit operation adjustment based on distributed on-chip temperature sensors

SUN MICROSYSTEMS INC14 citations84

US7054787B2May 30, 2006

Embedded integrated circuit aging sensor system

SUN MICROSYSTEMS INC16 citations84

US6894528B2May 17, 2005

Process monitor based keeper scheme for dynamic circuits

SUN MICROSYSTEMS INC15 citations84

US6814485B2Nov 9, 2004

On-die thermal monitoring technique

SUN MICROSYSTEMS INC17 citations84

US6628135B2Sep 30, 2003

Analog-based on-chip voltage sensor

SUN MICROSYSTEMS INC18 citations84

US6614287B1Sep 2, 2003

Calibration technique for delay locked loop leakage current

SUN MICROSYSTEMS INC18 citations84

US6597219B1Jul 22, 2003

Delay locked loop design with switch for loop filter capacitance leakage current control

SUN MICROSYSTEMS INC17 citations84

US6570420B1May 27, 2003

Programmable current source adjustment of leakage current for delay locked loop

SUN MICROSYSTEMS INC19 citations84

US6873503B2Mar 29, 2005

SSTL pull-up pre-driver design using regulated power supply

SUN MICROSYSTEMS INC13 citations82

US7062688B2Jun 13, 2006

Updating high speed parallel I/O interfaces based on counters

SUN MICROSYSTEMS INC10 citations74

US6788045B2Sep 7, 2004

Method and apparatus for calibrating a delay locked loop charge pump current

SUN MICROSYSTEMS INC9 citations74

US6768955B2Jul 27, 2004

Adjustment and calibration system for post-fabrication treatment of phase locked loop charge pump

SUN MICROSYSTEMS INC9 citations74

US6700390B2Mar 2, 2004

Adjustment and calibration system to store resistance settings to control chip/package resonance

SUN MICROSYSTEMS INC11 citations74

US6573770B1Jun 3, 2003

Programmable leakage current offset for delay locked loop

SUN MICROSYSTEMS INC10 citations74

US6570421B1May 27, 2003

Programmable leakage current offset for phase locked loop

SUN MICROSYSTEMS INC10 citations74

US6570422B1May 27, 2003

Phase locked loop design with switch for loop filter capacitance leakage current control

SUN MICROSYSTEMS INC10 citations74

US6552571B2Apr 22, 2003

Clock induced supply noise reduction apparatus for a latch based circuit

SUN MICROSYSTEMS INC7 citations74

US6549030B2Apr 15, 2003

Clock induced supply noise reduction method for a latch based circuit

SUN MICROSYSTEMS INC6 citations74

US6501328B1Dec 31, 2002

Method for reducing peak to peak jitter in a dual-loop delay locked loop

SUN MICROSYSTEMS INC9 citations74

US6483341B2Nov 19, 2002

CMOS-microprocessor chip and package anti-resonance apparatus

SUN MICROSYSTEMS INC9 citations74

US6456107B1Sep 24, 2002

CMOS-microprocessor chip and package anti-resonance method

SUN MICROSYSTEMS INC7 citations74

US6392443B1May 21, 2002

Power/area efficient method for high-frequency pre-emphasis for chip to chip signaling

SUN MICROSYSTEMS INC7 citations74

US6842057B1Jan 11, 2005

Analog state recovery technique for DLL design

SUN MICROSYSTEMS INC9 citations73

US6759877B1Jul 6, 2004

Dynamic circuitry with on-chip temperature-controlled keeper device

SUN MICROSYSTEMS INC7 citations73

US6734716B2May 11, 2004

SSTL pull-down pre-driver design using regulated power supply

SUN MICROSYSTEMS INC7 citations71

US6879929B2Apr 12, 2005

Sense amplifier thermal correction scheme

SUN MICROSYSTEMS INC5 citations70

US7106113B2Sep 12, 2006

Adjustment and calibration system for post-fabrication treatment of phase locked loop input receiver

SUN MICROSYSTEMS INC2 citations63

US7062662B2Jun 13, 2006

I/O resonance cancellation circuit based on charge-pumped capacitors

SUN MICROSYSTEMS INC3 citations63

US7043379B2May 9, 2006

Method for quantifying I/O chip/package resonance

SUN MICROSYSTEMS INC5 citations63

US7013254B2Mar 14, 2006

Low-complexity, high accuracy model of a CPU power distribution system

SUN MICROSYSTEMS INC6 citations63

Showing the top 50 of 80 patents by PatentIndex Score.

GAUTHIER CLAUDE R

Patents

Circuitry to support a power/area efficient method for high-frequency pre-emphasis for chip to chip signaling

Power/area efficient method for high-frequency pre-emphasis for intra-chip signaling

Compensation technique to mitigate aging effects in integrated circuit components

On-chip temperature measurement technique

Adaptive keeper sizing for dynamic circuits based on fused process corner data

Integrated temperature sensor

I/O receiver thermal correction scheme

Method and apparatus for I/O resonance compensation

Negative bias temperature instability correction technique for delay locked loop and phase locked loop bias generators

Source synchronous interface using variable digital data delay lines

I/O power supply resonance compensation technique

Deskewing global clock skew using localized DLLs

Programmable current source adjustment of leakage current for phase locked loop

Method for reducing supply noise near an on-die thermal sensor

Method and system for monitoring and profiling an integrated circuit die temperature

Controller for monitoring temperature

Two-pin thermal sensor calibration interface

Generating different delay ratios for a strobe delay

Dynamic calibration of I/O power supply level

Method and apparatus to store delay locked loop biasing parameters

Dynamic circuit operation adjustment based on distributed on-chip temperature sensors

Embedded integrated circuit aging sensor system

Process monitor based keeper scheme for dynamic circuits

On-die thermal monitoring technique

Analog-based on-chip voltage sensor

Calibration technique for delay locked loop leakage current

Delay locked loop design with switch for loop filter capacitance leakage current control

Programmable current source adjustment of leakage current for delay locked loop

SSTL pull-up pre-driver design using regulated power supply

Updating high speed parallel I/O interfaces based on counters

Method and apparatus for calibrating a delay locked loop charge pump current

Adjustment and calibration system for post-fabrication treatment of phase locked loop charge pump

Adjustment and calibration system to store resistance settings to control chip/package resonance

Programmable leakage current offset for delay locked loop

Programmable leakage current offset for phase locked loop

Phase locked loop design with switch for loop filter capacitance leakage current control

Clock induced supply noise reduction apparatus for a latch based circuit

Clock induced supply noise reduction method for a latch based circuit

Method for reducing peak to peak jitter in a dual-loop delay locked loop

CMOS-microprocessor chip and package anti-resonance apparatus

CMOS-microprocessor chip and package anti-resonance method

Power/area efficient method for high-frequency pre-emphasis for chip to chip signaling

Analog state recovery technique for DLL design

Dynamic circuitry with on-chip temperature-controlled keeper device

SSTL pull-down pre-driver design using regulated power supply

Sense amplifier thermal correction scheme

Adjustment and calibration system for post-fabrication treatment of phase locked loop input receiver

I/O resonance cancellation circuit based on charge-pumped capacitors

Method for quantifying I/O chip/package resonance

Low-complexity, high accuracy model of a CPU power distribution system