Inventor

AMICK BRIAN W

US45 patents

⚠️ This page may combine multiple inventors who share the name “AMICK BRIAN W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

AMICK BRIAN W

SUN MICROSYSTEMS INC

Integrated temperature sensor

Method and apparatus for I/O resonance compensation

Source synchronous interface using variable digital data delay lines

I/O power supply resonance compensation technique

Method for reducing supply noise near an on-die thermal sensor

Generating different delay ratios for a strobe delay

Analog-based on-chip voltage sensor

Calibration technique for delay locked loop leakage current

SSTL pull-up pre-driver design using regulated power supply

Differential sense amplifier latch for high common mode input

Updating high speed parallel I/O interfaces based on counters

Method and apparatus for calibrating a delay locked loop charge pump current

Adjustment and calibration system for post-fabrication treatment of phase locked loop charge pump

Adjustment and calibration system to store resistance settings to control chip/package resonance

Programmable leakage current offset for delay locked loop

Programmable leakage current offset for phase locked loop

Clock induced supply noise reduction apparatus for a latch based circuit

Clock induced supply noise reduction method for a latch based circuit

Method for reducing peak to peak jitter in a dual-loop delay locked loop

SSTL pull-down pre-driver design using regulated power supply

I/O resonance cancellation circuit based on charge-pumped capacitors

Method for quantifying I/O chip/package resonance

Low-complexity, high accuracy model of a CPU power distribution system

Low-complexity, high accuracy model of a CPU anti-resonance system

Method for reducing a magnitude of a rate of current change of an integrated circuit

Method and apparatus for calibration of a post-fabrication bias voltage tuning feature for self biasing phase locked loop

Reducing I/O supply noise with digital control

Apparatus for reducing the supply noise near large clock drivers

Clock noise reduction apparatus

Clock noise reduction method

Data transmission update technique in low power modes

SSTL voltage translator with dynamic biasing

Cascode SSTL output buffer using source followers

Method and apparatus for receiver circuit tuning

Technique to enlarge data eyes in wireline communication systems

Calibration technique for phase locked loop leakage current

System, method and apparatus for improving sense amplifier performance characteristics using process feedback

Method for smoothing dI/dT noise due to clock transitions

Round-robin updating for high speed I/O parallel interfaces

ADVANCED MICRO DEVICES INC

Dynamic RAM Phy interface with configurable power states

Dynamic RAM Phy interface with configurable power states

Method and apparatus for power-up detection for an electrical monitoring circuit

Method and apparatus of alternating service modes of an SOI process circuit

Method and apparatus for phase selection acceleration

CHO HANWOO

Memory diagnostics system and method with hardware-based read/write patterns