Inventor
SO KIMMING
US25 patents
⚠️ This page may combine multiple inventors who share the name “SO KIMMING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
13 patentsUS5584013ADec 10, 1996
Hierarchical cache arrangement wherein the replacement of an LRU entry in a second level cache is prevented when the cache entry is the only inclusive entry in the first level cache
IBM88 citations96
US5530832AJun 25, 1996
System and method for practicing essential inclusion in a multiprocessor and cache hierarchy
IBM80 citations96
US5048018ASep 10, 1991
Debugging parallel programs by serialization
IBM53 citations96
US4774654ASep 27, 1988
Apparatus and method for prefetching subblocks from a low speed memory to a high speed memory of a memory hierarchy depending upon state of replacing bit in the low speed memory
IBM59 citations96
US5133061AJul 21, 1992
Mechanism for improving the randomization of cache accesses utilizing abit-matrix multiplication permutation of cache addresses
IBM62 citations94
US6073211AJun 6, 2000
Method and system for memory updates within a multiprocessor data processing system
IBM51 citations92
US5897651AApr 27, 1999
Information handling system including a direct access set associative cache and method for accessing same
IBM21 citations92
US5694573ADec 2, 1997
Shared L2 support for inclusion property in split L1 data and instruction caches
IBM37 citations92
US5655103AAug 5, 1997
System and method for handling stale data in a multiprocessor system
IBM27 citations92
US5533189AJul 2, 1996
System and method for error correction code generation
IBM24 citations92
US5553253ASep 3, 1996
Correlation-based branch prediction in digital computers
IBM46 citations91
US5692151ANov 25, 1997
High performance/low cost access hazard detection in pipelined cache controller using comparators with a width shorter than and independent of total width of memory address
IBM13 citations73
US5699538ADec 16, 1997
Efficient firm consistency support mechanisms in an out-of-order execution superscaler multiprocessor
IBM9 citations68
BROADCOM CORP
11 patentsUS6944746B2Sep 13, 2005
RISC processor supporting one or more uninterruptible co-processors
BROADCOM CORP68 citations98
US6957306B2Oct 18, 2005
System and method for controlling prefetching
BROADCOM CORP45 citations94
US6963613B2Nov 8, 2005
Method of communicating between modules in a decoding system
BROADCOM CORP48 citations92
US8356158B2Jan 15, 2013
Mini-translation lookaside buffer for use in memory translation
BROADCOM CORP6 citations80
US6931494B2Aug 16, 2005
System and method for directional prefetching
BROADCOM CORP4 citations72
US7386646B2Jun 10, 2008
System and method for interrupt distribution in a multithread processor
BROADCOM CORP7 citations67
US7167954B2Jan 23, 2007
System and method for caching
BROADCOM CORP2 citations61
US7617380B2Nov 10, 2009
System and method for synchronizing translation lookaside buffer access in a multithread processor
BROADCOM CORP5 citations56
US7711906B2May 4, 2010
System and method for caching
BROADCOM CORP0 citations51
US7627720B2Dec 1, 2009
System and method for directional prefetching
BROADCOM CORP0 citations51
US7111127B2Sep 19, 2006
System for supporting unlimited consecutive data stores into a cache memory
BROADCOM CORP0 citations42