Inventor

FOSSUM TRYGGVE

US42 patents

⚠️ This page may combine multiple inventors who share the name “FOSSUM TRYGGVE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FOSSUM TRYGGVE

DIGITAL EQUIPMENT CORP

Method and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elements

Branch prediction

System for delaying processing of memory access exceptions until the execution stage of an instruction pipeline of a virtual memory system based digital computer

Method and apparatus for ordering and queueing multiple memory requests

Scheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor system

System for arbitrating communication requests using multi-pass control unit based on availability of system resources

Method and apparatus for simultaneously decoding three operands in a variable length instruction when one of the operands is also of variable length

Method and apparatus for resolving a variable number of potential memory access conflicts in a pipelined computer system

Write back buffer with error correcting capabilities

Control of multiple functional units with parallel operation in a microcoded execution unit

Integrated circuit chip having primary and secondary random access memories for a hierarchical cache

Method and apparatus for handling faults of vector instructions causing memory management exceptions

Method and apparatus using a source operand list and a source operand pointer queue between the execution unit and the instruction decoding and operand processing units of a pipelined data processor

Method and apparatus for detecting and correcting errors in a pipelined computer system

Apparatus and method for intelligent multiple-probe cache allocation

System for translation of virtual to physical addresses by operating memory management processor for calculating location of physical address in memory concurrently with cache comparing virtual addresses for translation

Synchronizing and processing of memory access operations in multiprocessor systems using a directory of lock bits

Instruction prefetch system for conditional branch instruction for central processor unit

Memory device for storing vector registers

System for queuing individual read or write mask and generating respective composite mask for controlling access to general purpose register

Pipelined floating point adder for digital computer

Method and apparatus for executing instructions for a vector processing system

Method and apparatus for self-testing of floating point accelerator processors

Microcode control system for digital data processing system

INTEL CORP

Method, system, and apparatus for improving multi-core processor performance

Method, system, and apparatus for improving multi-core processor performance

Scalable multi-layer 2D-mesh routers

Method, system, and apparatus for improving multi-core processor performance

Hardware compilation and/or translation with fault detection and roll back functionality

Converting merge buffer system-kill errors to process-kill errors

Low energy consumption mantissa multiplication for floating point multiply-add operations

Method of handling errors

Distributed power management for multi-core processors

FOSSUM TRYGGVE

Apparatus and method for heterogeneous chip multiprocessors via resource allocation and restriction

Shared cache performance

Apparatus and method for heterogeneous chip multiprocessors via resource allocation and restriction

COMPAQ INFORMATION TECHNOLOGIE

Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unit

HEWLETT PACKARD DEVELOPMENT CO

Temporary halting of thread execution until monitoring of armed events to memory location identified in working registers

DIGITAL EQUIPMENT

Vector register system for executing plural read/write commands concurrently and independently routing data to plural read/write ports

HASENPLAUGH WILLIAM

Technique for controlling computing resources

ILLIKKAL RAMESH KUMAR

Priority based throttling for power/performance quality of service

CHEE NICHOLAS CHENG HWA

Hardware compilation and/or translation with fault detection and roll back functionality