Inventor
MAUER VOLKER
GB37 patents
⚠️ This page may combine multiple inventors who share the name “MAUER VOLKER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ALTERA CORP
26 patentsUS6998909B1Feb 14, 2006
Method to compensate for memory effect in lookup table based digital predistorters
ALTERA CORP61 citations96
US8751551B2Jun 10, 2014
Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry
ALTERA CORP32 citations94
US7814137B1Oct 12, 2010
Combined interpolation and decimation filter for programmable logic device
ALTERA CORP50 citations94
US6400290B1Jun 4, 2002
Normalization implementation for a logmap decoder
ALTERA CORP26 citations93
US7369637B1May 6, 2008
Adaptive sampling rate converter
ALTERA CORP26 citations92
US9337782B1May 10, 2016
Methods and apparatus for adjusting transmit signal clipping thresholds
ALTERA CORP43 citations91
US9036734B1May 19, 2015
Methods and apparatus for performing digital predistortion using time domain and frequency domain alignment
ALTERA CORP27 citations87
US7948267B1May 24, 2011
Efficient rounding circuits and methods in configurable integrated circuit devices
ALTERA CORP15 citations84
US7039091B1May 2, 2006
Method and apparatus for implementing a two dimensional correlator
ALTERA CORP17 citations84
US8386550B1Feb 26, 2013
Method for configuring a finite impulse response filter in a programmable logic device
ALTERA CORP13 citations83
US9485129B1Nov 1, 2016
Multi-standard peak canceling circuitry
ALTERA CORP14 citations82
US7680233B1Mar 16, 2010
Adaptive sampling rate converter
ALTERA CORP6 citations74
US10136384B1Nov 20, 2018
Methods and apparatus for performing buffer fill level controlled dynamic power scaling
ALTERA CORP5 citations73
US9966933B1May 8, 2018
Pipelined systolic finite impulse response filter
ALTERA CORP2 citations73
US9748928B1Aug 29, 2017
Dynamically programmable digital signal processing blocks for finite-impulse-response filters
ALTERA CORP2 citations73
US9438203B1Sep 6, 2016
Dynamically programmable digital signal processing blocks for finite-impulse-response filters
ALTERA CORP3 citations73
US6944577B1Sep 13, 2005
Method and apparatus for extracting data from an oversampled bit stream
ALTERA CORP7 citations73
US9660624B1May 23, 2017
Methods and apparatus for implementing feedback loops
ALTERA CORP2 citations71
US9379687B1Jun 28, 2016
Pipelined systolic finite impulse response filter
ALTERA CORP2 citations63
US7095349B1Aug 22, 2006
Numerically controlled oscillator and method for operating the same
ALTERA CORP5 citations63
US6910056B1Jun 21, 2005
Method and apparatus for implementing a multi-step pseudo random sequence generator
ALTERA CORP3 citations63
US7586995B1Sep 8, 2009
Peak windowing for crest factor reduction
ALTERA CORP4 citations62
US7260154B1Aug 21, 2007
Method and apparatus for implementing a multiple constraint length Viterbi decoder
ALTERA CORP2 citations60
US8620977B1Dec 31, 2013
Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry
ALTERA CORP0 citations52
US8005177B1Aug 23, 2011
Peak windowing for crest factor reduction
ALTERA CORP0 citations52
US10003341B1Jun 19, 2018
Flexible input structure for arithmetic processing block
ALTERA CORP0 citations42
PAN ZHENGJUN
4 patentsUS8572456B1Oct 29, 2013
Avoiding interleaver memory conflicts
PAN ZHENGJUN6 citations71
US8583715B1Nov 12, 2013
Configuring a CIC filter in a programmable integrated circuit device
PAN ZHENGJUN2 citations60
US8291291B1Oct 16, 2012
Data resequencing
PAN ZHENGJUN1 citations48
US8578255B1Nov 5, 2013
Priming of metrics used by convolutional decoders
PAN ZHENGJUN0 citations39