Inventor

REN ZHIBIN

US47 patents

⚠️ This page may combine multiple inventors who share the name “REN ZHIBIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

REN ZHIBIN

IBM

Ultra thin body fully-depleted SOI MOSFETs

Ultra-thin body super-steep retrograde well (SSRW) FET devices

finFETS and methods of making same

Ion implantation combined with in situ or ex situ heat treatment for improved field effect transistors

Thin box metal backgate extremely thin SOI device

Structure and method of fabricating FinFET

Method and structure for enhancing both NMOSFET and PMOSFET performance with a stressed film

Ultra thin body fully-depleted SOI MOSFETs

Ultra-thin SOI CMOS with raised epitaxial source and drain and embedded SiGe PFET extension

Buried stress isolation for high-performance CMOS technology

Buried stress isolation for high-performance CMOS technology

Metal-gated MOSFET devices having scaled gate stack thickness including gettering species in a buried oxide

Metal-gated MOSFET devices having scaled gate stack thickness

Selective incorporation of charge for transistor channels

Asymmetric epitaxy and application thereof

Method and structure for enhancing both nMOSFET and pMOSFET performance with a stressed film

Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX)

Semiconductor-on-insulator substrate with a diffusion barrier

Uniaxial strain relaxation of biaxial-strained thin films using ion implantation

Method and structure for enhancing both nMOSFET and pMOSFET performance with a stressed film

Multi-kernel configuration for convolutional neural networks

Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX)

Ultrathin SOI CMOS devices employing differential STI liners

Aggregate adjustments in a cross bar neural network

Semiconductor-on-insulator(SOI) structures including gradient nitrided buried oxide (BOX)

Ultrathin SOI CMOS devices employing differential STI liners

Resistive processing unit cell having multiple weight update and read circuits for parallel processing of data using shared weight value

Selective incorporation of charge for transistor channels

Method for improving semiconductor surfaces

CHAN KEVIN K

Merged FinFETs and method of manufacturing the same

Thin-BOX metal backgate extremely thin SOI device

finFETs and methods of making same

Fabrication of field effect devices using spacers

CAI JIN

Method for fabricating super-steep retrograde well MOSFET on SOI or bulk silicon substrate, and device fabricated in accordance with the method

Method for fabricating super-steep retrograde well MOSFET on SOI or bulk silicon substrate, and device fabricated in accordance with the method

TAN YUE

Body contacts for FET in SOI SRAM array

Body contacts for FET in SOI SRAM array

REN ZHIBIN

Method for manufacturing a FinFET device comprising a mask to define a gate perimeter and another mask to define fin regions

Semiconductor devices with vertical extensions for lateral scaling

LI GUIHUA

Method, system and device for playing enterprise color ringback tone

Method, system and device for playing enterprise color ringback tone

DENNARD ROBERT H

Self-aligned well implant for improving short channel effects control, parasitic capacitance, and junction leakage

YIN HAIZHOU

Asymmetric epitaxy and application thereof

GLOBALFOUNDRIES INC

Conformal buffer layer in source and drain regions of fin-type transistors

CHOU ANTHONY I

Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX)

WISCONSIN ALUMNI RES FOUND

Uses of perillic acid methyl ester

LEOBANDUNG EFFENDI

High-k dielectric and silicon nitride box region