Inventor

JOURDAN STEPHAN J

US55 patents

⚠️ This page may combine multiple inventors who share the name “JOURDAN STEPHAN J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JOURDAN STEPHAN J

INTEL CORP

Instruction segment recording scheme

Register renaming to optimize identical register values

Correlated address prediction

Method and apparatus for dynamic branch prediction utilizing multiple stew algorithms for indexing a global history

Unified renaming scheme for load and store instructions

Mapping destination logical register to physical register storing immediate or renamed source register of move instruction and using mapping counters

Cache structure for storing variable length data

Return address stack including speculative return address buffer with back pointers

Cache structure for storing variable length data

Method and apparatus for rescheduling operations in a processor

Prediction of load-store dependencies in a processing agent

Generating lookahead tracked register value based on arithmetic operation indication

Cache memory bank access prediction

System and method for employing a global bit for page sharing in a linear-addressed cache

Enhanced virtual renaming scheme and deadlock prevention therefor

Method and system for safe data dependency collapsing based on control-flow speculation

Method and apparatus for reinforcing a prefetch chain

Method and apparatus for next-line prefetching from a predicted memory address

Method and apparatus for identifying candidate virtual addresses in a content-aware prefetcher

Register alias table cache to map a logical register to a physical register

Fusing load and alu operations

Method and apparatus for a register renaming structure

Predicting instruction branches with a plurality of global predictors using varying amounts of history instruction

Updating stack pointer based on instruction bit indicator without executing an update microinstruction

Method and apparatus for optimizing load memory accesses

Lookahead register value tracking

Memory record update filtering

System and method for employing a global bit for page sharing in a linear-addressed cache

Front end system having multiple decoding modes

Method and system for safe data dependency collapsing based on control-flow speculation

Sharing information to reduce redundancy in hybrid branch prediction

System and method for employing a process identifier to minimize aliasing in a linear-addressed cache

Memory cache bank prediction

Decoupling the number of logical threads from the number of simultaneous physical threads in a processor

Method and apparatus for content-aware prefetching

Retrieving data blocks with reduced linear addresses

Memory array with staged output

Enhanced virtual renaming scheme and deadlock prevention therefor

Late allocation of registers

Method and apparatus for predicting values in a processor having a plurality of prediction modes

Instruction segment filtering scheme

Memory record update filtering

Memory record update filtering

Memory cache bank prediction

Throttling integrated link

RADHAKRISHNAN SIVAKUMAR

Power measurement techniques of a system-on-chip (SOC)

TAN SIN S

Dynamic and idle power reduction sequence using recombinant clock and power gating

LOOI LILY PAO

Integration of processor and input/output hub

JOURDAN STEPHAN J

Method and apparatus for predicting branches using a meta predictor

RAJWAR RAVI

Throttling integrated link