Inventor

HARAN BALASUBRAMANIAN S

US82 patents

⚠️ This page may combine multiple inventors who share the name “HARAN BALASUBRAMANIAN S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HARAN BALASUBRAMANIAN S

IBM

Metal semiconductor alloy structure for low contact resistance

Bulk fin-field effect transistors with well defined isolation

Fin isolation in multi-gate field effect transistors

Bulk fin-field effect transistors with well defined isolation

Bulk fin-field effect transistors with well defined isolation

Integration of multiple threshold voltage devices for complementary metal oxide semiconductor using full metal gate

CMOS with dual raised source and drain for NMOS and PMOS

CMOS with dual raised source and drain for NMOS and PMOS

FinFET with dielectric isolation by silicon-on-nothing and method of fabrication

CMOS with dual raised source and drain for NMOS and PMOS

FinFET with dielectric isolation by silicon-on-nothing and method of fabrication

Dummy fin formation by gas cluster ion beam

Stress enhanced finFET devices

Uniform finFET gate height

Borderless contact for ultra-thin body devices

Cut first methodology for double exposure double etch integration

CMOS with dual raised source and drain for NMOS and PMOS

Method and structure for finFET with finely controlled device width

Stress enhanced finFET devices

CHENG KANGGUO

Bulk fin-field effect transistors with well defined isolation

Bulk fin-field effect transistors with well defined isolation

MOS capacitors with a finfet process

Method for integrating multiple threshold voltage devices for CMOS

CMOS with dual raised source and drain for NMOS and PMOS

FinFET with self-aligned punchthrough stopper

Suspended nanowire structure

Replacement gate ETSOI with sharp junction

Semiconductor devices with raised extensions

Semiconductor devices fabricated by doped material layer as dopant source

SOI device with embedded liner in box layer to limit STI recess

MOS capacitors with a finFET process

GLOBALFOUNDRIES INC

Dummy fin formation by gas cluster ion beam

Silicon-on-insulator transistor with self-aligned borderless source/drain contacts

FinFET with dielectric isolation by silicon-on-nothing and method of fabrication

HARAN BALASUBRAMANIAN S

Post-gate isolation area formation for fin field effect transistor device

Low resistance source and drain extensions for ETSOI

Method and structure for low resistive source and drain regions in a replacement metal gate process flow

BASKER VEERARAGHAVAN S

Cut-very-last dual-epi flow

Cut-very-last dual-EPI flow

EDGE LISA F

Borderless contact for replacement gate employing selective deposition

Dual metal fill and dual threshold voltage for replacement gate metal devices

STANDAERT THEODORUS EDUARDUS

FinFET diode with increased junction area

FinFET with improved gate planarity

KHAKIFIROOZ ALI

Local interconnect structure self-aligned to gate structure

CHEN KANGGUO

Method to form low series resistance transistor devices on silicon on insulator layer

DORIS BRUCE B

Shallow trench isolation structures

Globalfoundries

FinFET device

FAN SUSAN S

Method for fabricating silicon-on-insulator transistor with self-aligned borderless source/drain contacts

GLOBALFOUNDRIES US INC

Hybrid orientation fin field effect transistor and planar field effect transistor

ADAM THOMAS N

Semiconductor substrate with transistors having different threshold voltages