Inventor
SUNDARARAJAN PRASANNA
US38 patents
⚠️ This page may combine multiple inventors who share the name “SUNDARARAJAN PRASANNA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
XILINX INC
21 patentsUS7328335B1Feb 5, 2008
Bootable programmable logic device for internal decoding of encoded configuration data
XILINX INC94 citations98
US6668237B1Dec 23, 2003
Run-time reconfigurable testing of programmable logic devices
XILINX INC161 citations98
US6920627B2Jul 19, 2005
Reconfiguration of a programmable logic device using internal control
XILINX INC216 citations97
US7971072B1Jun 28, 2011
Secure exchange of IP cores
XILINX INC43 citations94
US7764081B1Jul 27, 2010
Programmable logic device (PLD) with memory refresh based on single event upset (SEU) occurrence to maintain soft error immunity
XILINX INC51 citations94
US7689726B1Mar 30, 2010
Bootable integrated circuit device for readback encoding of configuration data
XILINX INC53 citations94
US7852107B1Dec 14, 2010
Single event upset mitigation
XILINX INC21 citations92
US7788502B1Aug 31, 2010
Method and system for secure exchange of IP cores
XILINX INC35 citations92
US7406673B1Jul 29, 2008
Method and system for identifying essential configuration bits
XILINX INC31 citations92
US7386826B1Jun 10, 2008
Using redundant routing to reduce susceptibility to single event upsets in PLD designs
XILINX INC17 citations92
US7343578B1Mar 11, 2008
Method and system for generating a bitstream view of a design
XILINX INC30 citations92
US7249010B1Jul 24, 2007
Methods of estimating susceptibility to single event upsets for a design implemented in an FPGA
XILINX INC31 citations92
US7111215B1Sep 19, 2006
Methods of reducing the susceptibility of PLD designs to single event upsets
XILINX INC15 citations92
US6530071B1Mar 4, 2003
Method and apparatus for tolerating defects in a programmable logic device using runtime parameterizable cores
XILINX INC37 citations92
US7227378B2Jun 5, 2007
Reconfiguration of a programmable logic device using internal control
XILINX INC15 citations91
US7813912B1Oct 12, 2010
Profiling a hardware system generated by compiling a high level language onto a programmable logic device
XILINX INC11 citations84
US7539914B1May 26, 2009
Method of refreshing configuration data in an integrated circuit
XILINX INC11 citations84
US7930662B1Apr 19, 2011
Methods for automatically generating fault mitigation strategies for electronic system designs
XILINX INC10 citations83
US7519823B1Apr 14, 2009
Concealed, non-intrusive watermarks for configuration bitstreams
XILINX INC14 citations83
US7367007B1Apr 29, 2008
Method of routing a design to increase the quality of the design
XILINX INC9 citations81
US6665766B1Dec 16, 2003
Adaptable configuration interface for a programmable logic device
XILINX INC10 citations74
RENIAC INC
8 patentsUS9286221B1Mar 15, 2016
Heterogeneous memory system
RENIAC INC25 citations93
US10049035B1Aug 14, 2018
Stream memory management unit (SMMU)
RENIAC INC13 citations83
US9262325B1Feb 16, 2016
Heterogeneous memory system
RENIAC INC7 citations83
US11126600B2Sep 21, 2021
System and method to accelerate compaction
RENIAC INC1 citations61
US10931587B2Feb 23, 2021
Systems and methods for congestion control in a network
RENIAC INC1 citations61
US9043557B1May 26, 2015
Heterogeneous memory system
RENIAC INC2 citations61
US11044314B2Jun 22, 2021
System and method for a database proxy
RENIAC INC0 citations52
US10237350B2Mar 19, 2019
System and method for a database proxy
RENIAC INC0 citations42
SUNDARARAJAN PRASANNA
5 patentsUS8468510B1Jun 18, 2013
Optimization of cache architecture generated from a high-level language description
SUNDARARAJAN PRASANNA27 citations92
US9378003B1Jun 28, 2016
Compiler directed cache coherence for many caches generated from high-level language source code
SUNDARARAJAN PRASANNA21 citations91
US8104011B1Jan 24, 2012
Method of routing a design to increase the quality of the design
SUNDARARAJAN PRASANNA7 citations80
US8443344B1May 14, 2013
Methods for identifying gating opportunities from a high-level language program and generating a hardware definition
SUNDARARAJAN PRASANNA3 citations62
US8473904B1Jun 25, 2013
Generation of cache architecture from a high-level language description
SUNDARARAJAN PRASANNA3 citations56