Inventor
LEVY MARK D
US39 patents
⚠️ This page may combine multiple inventors who share the name “LEVY MARK D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
GLOBALFOUNDRIES US INC
30 patentsUS11972999B2Apr 30, 2024
Unlanded thermal dissipation pillar adjacent active contact
GLOBALFOUNDRIES US INC2 citations73
US11536914B2Dec 27, 2022
Photodetector array with diffraction gratings having different pitches
GLOBALFOUNDRIES US INC2 citations73
US11422303B2Aug 23, 2022
Waveguide with attenuator
GLOBALFOUNDRIES US INC2 citations73
US11152520B1Oct 19, 2021
Photodetector with reflector with air gap adjacent photodetecting region
GLOBALFOUNDRIES US INC4 citations73
US11316064B2Apr 26, 2022
Photodiode and/or PIN diode structures
GLOBALFOUNDRIES US INC4 citations72
US12538550B2Jan 27, 2026
High-electron-mobility transistor with field plate and sidewall spacers
GLOBALFOUNDRIES US INC0 citations62
US12342626B2Jun 24, 2025
Switches in bulk substrate
GLOBALFOUNDRIES US INC0 citations62
US12142686B2Nov 12, 2024
Field effect transistor
GLOBALFOUNDRIES US INC1 citations62
US12046633B2Jul 23, 2024
Airgap structures in auto-doped region under one or more transistors
GLOBALFOUNDRIES US INC0 citations62
US11881506B2Jan 23, 2024
Gate structures with air gap isolation features
GLOBALFOUNDRIES US INC0 citations62
US11611002B2Mar 21, 2023
Photodiode and/or pin diode structures
GLOBALFOUNDRIES US INC0 citations62
US11605649B2Mar 14, 2023
Switches in bulk substrate
GLOBALFOUNDRIES US INC0 citations62
US11588056B2Feb 21, 2023
Structure with polycrystalline active region fill shape(s), and related method
GLOBALFOUNDRIES US INC0 citations62
US11581450B2Feb 14, 2023
Photodiode and/or pin diode structures with one or more vertical surfaces
GLOBALFOUNDRIES US INC0 citations62
US11502214B2Nov 15, 2022
Photodetectors used with broadband signal
GLOBALFOUNDRIES US INC0 citations62
US11322639B2May 3, 2022
Avalanche photodiode
GLOBALFOUNDRIES US INC1 citations62
US11282740B2Mar 22, 2022
Bulk semiconductor structure with a multi-level polycrystalline semiconductor region and method
GLOBALFOUNDRIES US INC1 citations62
US11152394B1Oct 19, 2021
Structure with polycrystalline isolation region below polycrystalline fill shape(s) and selective active device(s), and related method
GLOBALFOUNDRIES US INC0 citations62
US12339247B2Jun 24, 2025
Field effect transistor with buried fluid-based gate and method
GLOBALFOUNDRIES US INC0 citations61
US12183814B1Dec 31, 2024
Multi-channel transistor
GLOBALFOUNDRIES US INC0 citations61
US12119383B2Oct 15, 2024
Transistor with multi-level self-aligned gate and source/drain terminals and methods
GLOBALFOUNDRIES US INC0 citations61
US11646351B2May 9, 2023
Transistor with multi-level self-aligned gate and source/drain terminals and methods
GLOBALFOUNDRIES US INC0 citations61
US12491511B2Dec 9, 2025
Microfluidic channel structure and method
GLOBALFOUNDRIES US INC0 citations60
US12411105B2Sep 9, 2025
Semiconductor structure with frontside port and cavity features for conveying sample to sensing element
GLOBALFOUNDRIES US INC0 citations59
US12154956B1Nov 26, 2024
Structure including multi-level field plate and method of forming the structure
GLOBALFOUNDRIES US INC0 citations59
US11978661B2May 7, 2024
Ultralow-K dielectric-gap wrapped contacts and method
GLOBALFOUNDRIES US INC0 citations56
US12581701B2Mar 17, 2026
Device with dual isolation structure
GLOBALFOUNDRIES US INC0 citations52
US12557323B2Feb 17, 2026
Enhancement mode transistor with a robust gate and method
GLOBALFOUNDRIES US INC0 citations52
US12062574B2Aug 13, 2024
Integrated circuit structure with through-metal through-substrate interconnect and method
GLOBALFOUNDRIES US INC0 citations51
US12281996B2Apr 22, 2025
Semiconductor structure including photodiode-based fluid sensor and methods
GLOBALFOUNDRIES US INC0 citations50
IBM
6 patentsUS7823106B2Oct 26, 2010
Variable performance ranking and modification in design for manufacturability of circuits
IBM26 citations89
US9059233B2Jun 16, 2015
Formation of an asymmetric trench in a semiconductor substrate and a bipolar semiconductor device having an asymmetric trench isolation region
IBM4 citations72
US9231089B2Jan 5, 2016
Formation of an asymmetric trench in a semiconductor substrate and a bipolar semiconductor device having an asymmetric trench isolation region
IBM2 citations62
US7087997B2Aug 8, 2006
Copper to aluminum interlayer interconnect using stud and via liner
IBM4 citations61
US7037824B2May 2, 2006
Copper to aluminum interlayer interconnect using stud and via liner
IBM2 citations61
US7060626B2Jun 13, 2006
Multi-run selective pattern and etch wafer process
IBM5 citations55