Inventor

FERRAIOLO FRANK D

US72 patents

⚠️ This page may combine multiple inventors who share the name “FERRAIOLO FRANK D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FERRAIOLO FRANK D

IBM

System, method and storage medium for providing segment level sparing

Input-output element has self timed interface using a received clock signal to individually phase aligned bits received from a parallel bus

Circuit and method for reading data transfers that are sent with a source synchronous clock signal

Data edge phase sorting circuits

Method for transferring data between processors on a network by establishing an address space for each processor in each other processor&#39;s

Clock signal latency elimination network

System, method and storage medium for bus calibration in a memory subsystem

Glitch free delay line multiplexing technique

276-pin buffered memory module with enhanced fault tolerance

276-Pin buffered memory module with enhanced fault tolerance and a performance-optimized pin assignment

On-chip detection of power supply vulnerabilities

Data receiver with a programmable reference voltage to optimize timing jitter

Thevenins receiver

Delay equalization apparatus and method

Anti-latching mechanism for phase lock loops

Self-timed parallel inter-system data communication channel

Shared channel subsystem has a self timed interface using a received clock signal to individually phase align bits received from a parallel bus

Digital data link performance monitor

Digital integrating clock extractor

Self-timed circuit having critical path timing detection

Self timed interface

Circuit for converting between serial and parallel data streams by high speed addressing

Current reference circuit

Edge detector

Tunable inductor

Method and system for selecting data sampling phase for self timed interface logic

Digital delay line with low insertion delay

Self-healing chip-to-chip interface

Phase interpolator system and associated methods

Dynamic segment sparing and repair in a memory system

Dynamic recalibration mechanism for elastic interface

Combined alignment scrambler function for elastic interface

Signal transmission system with programmable voltage reference

On-chip detection of power supply vulnerabilities

System, method and storage medium for testing a memory module

276-pin buffered memory module with enhanced fault tolerance

System, method and storage medium for deriving clocks in a memory system

276-pin buffered memory module with enhanced fault tolerance

All FET fully integrated current reference circuit

On-chip detection of power supply vulnerabilities

Method for receiver delay detection and latency minimization for a source synchronous wave pipelined interface

Apparatus and method for recalibrating a source-synchronous pipelined self-timed bus interface

Edge detector

Method of testing a protocol converter with the help of an identical converter and deactivating selection means for preventing asymmetry conversion

Bus interface optimization by selecting bit-lanes having best performance margins

BAUMGARTNER STEVEN J

Parallel data communications mechanism having reduced power continuously calibrated lines

BUCHMANN PETER L

Power-on initialization and test for a cascade interconnect memory system

BULZACCHELLI JOHN F

Calibration of multiple parallel data communications lines for high skew conditions

FERRAIOLO FRANK D

Dynamic fault detection and repair in a data communications mechanism

DODSON JOHN S

Isolation of faulty links in a transmission medium

Method for transferring data between processors on a network by establishing an address space for each processor in each other processor's