Inventor

HARIDASS ANAND

IN91 patents

⚠️ This page may combine multiple inventors who share the name “HARIDASS ANAND”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HARIDASS ANAND

IBM

Self-healing chip-to-chip interface

Multi-layer circuit substrate and method having improved transmission line integrity and increased routing density

Method for detecting noise events in systems with time variable operating points

Programmable driver delay

Thevenins receiver

Apparatus and method for customized burn-in of cores on a multicore microprocessor integrated circuit chip

System and method to optimize multi-core microprocessor performance using voltage offsets

Multiple level computer system for temperature management for cooling fan control

Multiple level computer system temperature management for cooling fan control

Self-healing chip-to-chip interface

Self-healing chip-to-chip interface

Design method and system for minimizing blind via current loops

Mitigate power supply noise response by throttling execution units based upon voltage sensing

Apparatus and method for far end noise reduction using capacitive cancellation by offset wiring

Circuit for generating a tracking reference voltage

Statistical switched capacitor droop sensor for application in power distribution noise mitigation

Power grid structure to optimize performance of a multiple core processor

Uniform power density across processor cores at burn-in

Design techniques for analyzing integrated circuit device characteristics

Boundary scannable one bit precompensated CMOS driver with compensating pulse width control

System and method for noise reduction in multi-layer ceramic packages

System and method for automatic insertion of on-chip decoupling capacitors

Differential transmitter circuit

Leakage power characterization at high temperatures for an integrated circuit

Formal verification driven power modeling and design verification

Formal verification driven power modeling and design verification

System for reducing cross-talk induced source synchronous bus clock jitter

NVDIMM security with physically unclonable functions

System to monitor computing hardware in a computing infrastructure facility

Memory power management and data consolidation

Bus interface optimization by selecting bit-lanes having best performance margins

Characterization and validation of processor links

Multi-layer circuit substrate fabrication method providing improved transmission line integrity and increased routing density

System for designing substrates having reference plane voids with strip segments

Self-healing chip-to-chip interface

Reference plane voids with strip segment for improving transmission line integrity over vias

Method and computer program product for designing power distribution system in a circuit

Characterization and validation of processor links

Method for detecting noise events in systems with time variable operating points

Differential transmitter circuit

Power grid structure to optimize performance of a multiple core processor

Fabricating substrates having low inductance via arrangements

Via/BSM pattern optimization to reduce DC gradients and pin current density on single and multi-chip modules

Reduced cross-talk signaling circuit and method

Leakage power characterization at high temperatures for an integrated circuit

System DC Analysis Methodology

CHOI JINWOO

Noise coupling reduction and impedance discontinuity control in high-speed ceramic modules

Noise coupling reduction and impedance discontinuity control in high-speed ceramic modules

CHUN SUNGJUN

Multi-layer circuit substrate fabrication and design methods providing improved transmission line integrity and increased routing density

BERRY JR ROBERT W

Characterization and validation of processor links