Inventor
BERKOVITZ ASHER
IL14 patents
⚠️ This page may combine multiple inventors who share the name “BERKOVITZ ASHER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
SOFER SERGEY
4 patentsUS10746795B2Aug 18, 2020
Method and apparatus for at-speed scan shift frequency test optimization
SOFER SERGEY3 citations72
US9709629B2Jul 18, 2017
Method and control device for launch-off-shift at-speed scan testing
SOFER SERGEY3 citations72
US9903916B2Feb 27, 2018
Scan test system with a test interface having a clock control unit for stretching a power shift cycle
SOFER SERGEY1 citations51
US9977849B2May 22, 2018
Method and apparatus for calculating delay timing values for an integrated circuit design
SOFER SERGEY0 citations41
BERKOVITZ ASHER
4 patentsUS9836567B2Dec 5, 2017
Method of simulating a semiconductor integrated circuit, computer program product, and device for simulating a semiconductor integrated circuit
BERKOVITZ ASHER3 citations65
US9171117B2Oct 27, 2015
Method for ranking paths for power optimization of an integrated circuit design and corresponding computer program product
BERKOVITZ ASHER3 citations57
US9607117B2Mar 28, 2017
Method and apparatus for calculating delay timing values for an integrated circuit design
BERKOVITZ ASHER0 citations50
US9792399B2Oct 17, 2017
Integrated circuit hierarchical design tool apparatus and method of hierarchically designing an integrated circuit
BERKOVITZ ASHER0 citations28
FREESCALE SEMICONDUCTOR INC
3 patentsUS9652572B2May 16, 2017
Method and apparatus for performing logic synthesis
FREESCALE SEMICONDUCTOR INC0 citations47
US9038006B2May 19, 2015
Method and apparatus for generating gate-level activity data for use in clock gating efficiency analysis
FREESCALE SEMICONDUCTOR INC1 citations44
US10102329B2Oct 16, 2018
Method and apparatus for validating a test pattern
FREESCALE SEMICONDUCTOR INC0 citations40