Inventor

FREY BRADLY G

US43 patents

⚠️ This page may combine multiple inventors who share the name “FREY BRADLY G”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FREY BRADLY G

IBM

Coordination of out-of-sequence fetching between multiple processors using re-execution of instructions

Efficient enforcement of barriers with respect to memory move sequences

Translation entry invalidation in a multithreaded data processing system

Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spaces

Method and system for efficient bus allocation in a multimedia computer system

Hardware based isolation for secure execution of virtual machines

Translation entry invalidation in a multithreaded data processing system

Push instruction for pushing a message payload from a sending thread to a receiving thread

Interaction of transactional storage accesses with other atomic semantics

Managing translation of a same address across multiple contexts using a same entry in a translation lookaside buffer

Retaining an association between a virtual address based buffer and a user space application that owns the buffer

Interruptible translation entry invalidation in a multithreaded data processing system

Selectable address translation mechanisms

Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spaces

Rewind only transactions in a data processing system supporting transactional storage accesses

Mechanisms for eliminating a race condition between a hypervisor-performed emulation process requiring a translation operation and a concurrent translation table entry invalidation

Translation load instruction with access protection

Operation of a multi-slice processor implementing adaptive prefetch control

Hardware-based pre-page walk virtual address transformation independent of page size utilizing bit shifting based on page size

Efficient enforcement of barriers with respect to memory move sequences

Operation of a multi-slice processor implementing adaptive prefetch control

Hardware-based pre-page walk virtual address transformation where the virtual address is shifted by current page size and a minimum page size

Memory move instruction sequence including a stream of copy-type and paste-type instructions

Push instruction for pushing a message payload from a sending thread to a receiving thread

Transaction check instruction for memory transactions

Transaction check instruction for memory transactions

Managing translation of a same address across multiple contexts using a same entry in a translation lookaside buffer

Determining failure context in hardware transactional memories

Asymmetric co-existent address translation structure formats

Asymmetric co-existent address translation structure formats

Virtual unifed instruction and data caches including storing program instructions and memory address in CAM indicated by store instruction containing bit directly indicating self modifying code

Nested rewind only and non rewind only transactions in a data processing system supporting transactional storage accesses

Conditional transaction abort and precise abort handling

ARNDT RICHARD L

Transactional memory preemption mechanism

Transactional memory preemption mechanism

BRUCE BECKY

Indicating disabled thread to other threads when contending instructions complete execution to ensure safe shared resource condition

Processor with hardware thread control logic indicating disable status when instructions accessing shared resources are completed for safe shared resource condition

FREY BRADLY G

Ensuring causality of transactional storage accesses interacting with non-transactional storage accesses

Specifying an access hint for prefetching limited use data in a cache hierarchy

CAIN III HAROLD W

Transactional memory system supporting unbroken suspended execution

BLAINEY ROBERT J

Recording and profiling transaction failure source addresses and states of validity indicator corresponding to addresses of aborted transaction in hardware transactional memories

CAIN HAROLD W

Apparatus for determining failure context in hardware transactional memories

DALE JASON N

Persistent prefetch data stream settings