Inventor

KRYGOWSKI CHRISTOPHER A

US58 patents

⚠️ This page may combine multiple inventors who share the name “KRYGOWSKI CHRISTOPHER A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KRYGOWSKI CHRISTOPHER A

IBM

Method, system and computer program product for failure analysis implementing automated comparison of multiple reference models

Pipelined floating point stores

Method and system for executing denormalized numbers

Storage pre-alignment and EBCDIC, ASCII and unicode basic latin conversions for packed decimal data

IEEE compliant floating point unit

Variable acknowledge rate to reduce bus contention in presence of communication errors

Multi-pipe dispatch and execution of complex instructions in a superscalar processor

Superscalar microprocessor having multi-pipe dispatch and execution unit

Last iteration loop branch prediction upon counter threshold and resolution upon counter one

Floating point unit for multiple data architectures

Modular binary multiplier for signed and unsigned operands of variable widths

Confidence threshold-based opposing branch path execution for branch prediction

Confidence threshold-based opposing branch path execution for branch prediction

Thread sparing between cores in a multi-threaded processor

Modular binary multiplier for signed and unsigned operands of variable widths

Management of resources within a computing environment

Hardware recovery in multi-threaded processor

In situ processor re-characterization

Management of resources within a computing environment

Management of migrating threads within a computing environment to transform multiple threading mode processors to single thread mode processors

Decimal multiplication for superscaler processors

Decimal multiplication for superscaler processors

Method and system for determining quotient digits for decimal division in a superscaler processor

Floating-point multiplier for de-normalized inputs

Method, system, and computer program product for out of order instruction address stride prefetch performance verification

Functional testing of a processor design

Method, system and computer program product for exploiting orthogonal control vectors in timing driven synthesis

Management of resources within a computing environment

Dynamic accessing of execution elements through modification of issue rules

Anticipated prefetching for a parent core in a multi-core chip

Anticipated prefetching for a parent core in a multi-core chip

Management of resources within a computing environment

Dynamic accessing of execution elements through modification of issue rules

Major branch instructions

Major branch instructions with transactional memory

Thread sparing between cores in a multi-threaded processor

Specific prefetch algorithm for a chip having a parent core and a scout core

Specific prefetch algorithm for a chip having a parent core and a scout core

Prefetching for multiple parent cores in a multi-core chip

Prefetching for multiple parent cores in a multi-core chip

Prefetching for a parent core in a multi-core chip

BUSABA FADI Y

Hardware recovery in multi-threaded processor

Reconfigurable recovery modes in high availability processors

Management of migrating threads within a computing environment to transform multiple threading mode processors to single thread mode processors

Variable acknowledge rate to reduce bus contention in presence of communication errors

In situ processor re-characterization

Management of resources within a computing environment

Cache set replacement order based on temporal set recording

Major branch instructions

Major branch instructions with transactional memory