Inventor

CHENG WU-TUNG

US86 patents

⚠️ This page may combine multiple inventors who share the name “CHENG WU-TUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHENG WU-TUNG

MENTOR GRAPHICS CORP

Built-in self-test of integrated circuits using selectable weighting of test patterns

Testing embedded memories in an integrated circuit

Cell-aware root cause deconvolution for defect diagnosis and yield analysis

Multi-stage test response compactors

Defect localization based on defective cell diagnosis

Test access architecture for stacked memory and logic dies

Hybrid memory failure bitmap classification

Generating root cause candidates for yield analysis

Chain testing and diagnosis using two-dimensional scan architecture

Low pin count reversible scan architecture

Prediction of test pattern counts for scan configuration determination

Cell-aware diagnostic pattern generation for logic diagnosis

Expanded canonical forms of layout patterns

Identification of power sensitive scan cells

Faulty chains identification without masking chain patterns

Enhanced diagnosis with limited failure cycles

Library cell modeling for transistor-level test pattern generation

CHENG WU-TUNG

Compactor independent fault diagnosis

Direct fault diagnostics using per-pattern compactor signatures

Removing the effects of unknown test values from compacted test responses

Removing the effects of unknown test values from compacted test responses

Accurately identifying failing scan bits in compression environments

Full-speed BIST controller for testing embedded synchronous memories

Built-in self-analyzer for embedded memory

Profiling-based scan chain diagnosis

Compactor independent fault diagnosis

HUANG YU

Compactor independent direct diagnosis of test hardware

Compactor independent direct diagnosis of test hardware

Diagnosing mixed scan chain and system logic defects

Two-dimensional scan architecture

Method and system for scan chain diagnosis

MUKHERJEE NILANJAN

Reduced-pin-count-testing architectures for applying test patterns

Flexible memory built-in-self-test (MBIST) method and apparatus

Programmable memory built-in-self-test (MBIST) method and apparatus

Performing memory built-in-self-test (MBIST)

GUO RUIFENG

Test pattern generation for diagnosing scan chain failures

Generating test sets for diagnosing scan chain failures

Fault dictionary-based scan chain failure diagnosis

Detection and diagnosis of scan cell internal defects

(unassigned)

Full-speed BIST controller for testing embedded synchronous memories

Method and apparatus for creating testable circuit designs having embedded cores

Scheduling the concurrent testing of multiple cores embedded in an integrated circuit

SIEMENS IND SOFTWARE INC

Bidirectional scan cells for single-path reversible scan chains

Programmable test compactor for improving defect determination

Machine learning-based adjustments in volume diagnosis procedures for determination of root cause distributions

KEBICHI OMAR

Synchronization point across different memory BIST controllers

Synchronization point across different memory BIST controllers

RAJSKI JANUSZ

Multi-stage test response compactors

RINDERKNECHT THOMAS HANS

Using constrained scan cells to test integrated circuits

ROSS DON E

Testing embedded memories in an integrated circuit