Inventor

CONTI RICHARD A

US65 patents

⚠️ This page may combine multiple inventors who share the name “CONTI RICHARD A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CONTI RICHARD A

IBM

Method for low temperature chemical vapor deposition of low-k films using selected cyclosiloxane and ozone gases for semiconductor applications

Method for low temperature chemical vapor deposition of low-k films using selected cyclosiloxane and ozone gases for semiconductor applications

Directional CVD process with optimized etchback

Aluminum oxide low pressure chemical vapor deposition (LPCVD) system-fourier transform infrared (FTIR) source chemical control

Carbon-graded layer for improved adhesion of low-k dielectrics to silicon substrates

Storage capacitor with a conducting oxide electrode for metal-oxide dielectrics

Methods and apparatus for filling high aspect ratio structures with silicate glass

Modified gate processing for optimized definition of array and logic devices on same chip

Modified gate processing for optimized definition of array and logic devices on same chip

HDP-based ILD capping layer

Carbon-graded layer for improved adhesion of low-k dielectrics to silicon substrates

Manufacturing of cavity fuses on gate conductor level

Apparatus for chemical vapor deposition of aluminum oxide

Safe method for etching silicon dioxide

Method of forming nitride films with high compressive stress for improved PFET device performance

Methods and materials for depositing films on semiconductor substrates

Multi-level air gap formation in dual-damascene structure

Borophosphosilicate glass incorporated with fluorine for low thermal budget gap fill

Aluminum oxide LPCVD system

Method for forming damascene structure utilizing planarizing material coupled with compressive diffusion barrier material

Stabilization of fluorine-containing dielectric materials in a metal insulator wiring structure

Self-aligned buried strap process using doped HDP oxide

Integrated circuits having reduced stress in metallization

Method for reducing stress in the metallization of an integrated circuit

LPCVD reactor for high efficiency, high uniformity deposition

Nanosheet transistor having a strained channel with strain-preserving multi-segmented source/drain regions

Stress modulation of nFET and pFET fin structures

Fluid delivery apparatus having an infrared feedline sensor

Fluid delivery apparatus and method having an infrared feedline sensor

Removable gas injectors for use in chemical vapor deposition of aluminium oxide

Multi-level air gap formation in dual-damascene structure

Multi-level air gap formation in dual-damascene structure

HDP-based ILD capping layer

Method of forming metal connections

Middle-of-line interconnect having low metal-to-metal interface resistance

Forming shallow trench isolation regions for nanosheet field-effect transistor devices using sacrificial epitaxial layer

Dual width finned semiconductor structure

Self-aligned gate contact integration with metal resistor

Forming shallow trench isolation regions for nanosheet field-effect transistor devices using sacrificial epitaxial layer

Stress modulation of nFET and pFET fin structures

Self-aligned buried strap process using doped HDP oxide

Low temperature LPCVD PSG/BPSG process

Nano multilayer carbon-rich low-k spacer

Nano multilayer carbon-rich low-k spacer

Protection of low temperature isolation fill

Method of eliminating a critical mask using a blockout mask and a resulting semiconductor structure

NOVELLUS SYSTEMS INC

High throughput chemical vapor deposition process capable of filling high aspect ratio structures

INFINEON TECHNOLOGIES AG

Low temperature carbon rich oxy-nitride for improved RIE selectivity

APPLIED MATERIALS INC

BPSG reflow method to reduce thermal budget for next generation device including heating in a steam ambient

O'MEARA DAVID L

Multilayer sidewall spacer for seam protection of a patterned structure