Inventor

DUTTA AMIT KUMAR

US12 patents

⚠️ This page may combine multiple inventors who share the name “DUTTA AMIT KUMAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MICROSOFT TECHNOLOGY LICENSING LLC

5 patents

US10187439B2Jan 22, 2019

TEXAS INSTRUMENTS INC

1 patent

US8671329B2Mar 11, 2014

Low overhead and timing improved architecture for performing error checking and correction for memories and buses in system-on-chips, and other circuits, systems and processes

TEXAS INSTRUMENTS INC17 citations92

KUMAR SANJAY

1 patent

US8438344B2May 7, 2013

Low overhead and timing improved architecture for performing error checking and correction for memories and buses in system-on-chips, and other circuits, systems and processes

KUMAR SANJAY19 citations91

GANGASANI SWATHI

1 patent

US8286042B2Oct 9, 2012

On-chip seed generation using boolean functions for LFSR re-seeding based logic BIST techniques for low cost field testability

GANGASANI SWATHI17 citations77

FACEBOOK INC

1 patent

US10757259B1Aug 25, 2020

Custom calling using a messaging system

FACEBOOK INC1 citations60

NXP BV

1 patent

US11025295B2Jun 1, 2021

Optimizing MRC coefficients for RAKE receiver for increasing SNR

NXP BV0 citations55

MICROSOFT CORP

1 patent

US8983041B2Mar 17, 2015

Conserving call logic during handoff

MICROSOFT CORP0 citations50

DUTTA AMIT KUMAR

1 patent

US8547931B2Oct 1, 2013

Conserving call logic during handoff

DUTTA AMIT KUMAR1 citations44

DUTTA AMIT KUMAR

MICROSOFT TECHNOLOGY LICENSING LLC

Dynamic recording of online conference

Joining executable component to online conference

Joining executable component to online conference

Per-stage assignment of pipelines agents

Text translation of an audio recording during recording capture

TEXAS INSTRUMENTS INC

Low overhead and timing improved architecture for performing error checking and correction for memories and buses in system-on-chips, and other circuits, systems and processes

KUMAR SANJAY

Low overhead and timing improved architecture for performing error checking and correction for memories and buses in system-on-chips, and other circuits, systems and processes

GANGASANI SWATHI

On-chip seed generation using boolean functions for LFSR re-seeding based logic BIST techniques for low cost field testability

FACEBOOK INC

Custom calling using a messaging system

NXP BV

Optimizing MRC coefficients for RAKE receiver for increasing SNR

MICROSOFT CORP

Conserving call logic during handoff

DUTTA AMIT KUMAR

Conserving call logic during handoff