P

Inventor

FRYMAN JOSHUA B

US22 patents
⚠️ This page may combine multiple inventors who share the name “FRYMAN JOSHUA B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

19 patents
US9477628B2Oct 25, 2016

Collective communications apparatus and method for parallel systems

INTEL CORP6 citations71
US10684858B2Jun 16, 2020

Indirect memory fetcher

INTEL CORP2 citations70
US10409763B2Sep 10, 2019

Apparatus and method for efficiently implementing a processor pipeline

INTEL CORP6 citations70
US10795819B1Oct 6, 2020

Multi-processor system with configurable cache sub-domains and cross-die memory coherency

INTEL CORP4 citations69
US11061742B2Jul 13, 2021

System, apparatus and method for barrier synchronization in a multi-threaded processor

INTEL CORP2 citations67
US12455738B2Oct 28, 2025

Large-scale matrix restructuring and matrix-scalar operations

INTEL CORP1 citations61
US11960922B2Apr 16, 2024

System, apparatus and method for user space object coherency in a processor

INTEL CORP0 citations61
US7984244B2Jul 19, 2011

Method and apparatus for supporting scalable coherence on many-core products through restricted exposure

INTEL CORP3 citations61
US12388712B2Aug 12, 2025

In-network multicast operations

INTEL CORP0 citations60
US11630691B2Apr 18, 2023

Memory system architecture for multi-threaded processors

INTEL CORP0 citations58
US11106494B2Aug 31, 2021

Memory system architecture for multi-threaded processors

INTEL CORP0 citations58
US10296338B2May 21, 2019

System, apparatus and method for low overhead control transfer to alternate address space in a processor

INTEL CORP1 citations57
US11308006B2Apr 19, 2022

Memory rank design for a memory channel that is optimized for graph applications

INTEL CORP0 citations54
US12436314B2Oct 7, 2025

Technologies for chip-to-chip optical data transfer background

INTEL CORP0 citations52
US9405724B2Aug 2, 2016

Reconfigurable apparatus for hierarchical collective networks with bypass mode

INTEL CORP1 citations52
US12554906B2Feb 17, 2026

Low latency and highly programmable interrupt controller unit

INTEL CORP0 citations50
US10942851B2Mar 9, 2021

System, apparatus and method for dynamic automatic sub-cacheline granularity memory access control

INTEL CORP0 citations49
US11526483B2Dec 13, 2022

Storage architectures for graph analysis applications

INTEL CORP0 citations47
US12455741B2Oct 28, 2025

Low overhead error correction code

INTEL CORP0 citations45

FRYMAN JOSHUA B

3 patents