Inventor

POISNER DAVID I

US98 patents

Patents

50 patents

US5729760AMar 17, 1998

System for providing first type access to register if processor in first mode and second type access to register if processor not in first mode

INTEL CORP220 citations99

US6920553B1Jul 19, 2005

Method and apparatus for reading initial boot instructions from a bootable device connected to the USB port of a computer system

INTEL CORP84 citations98

US7149909B2Dec 12, 2006

Power management for an integrated graphics device

INTEL CORP71 citations96

US6842776B1Jan 11, 2005

Method for automatic device monitoring by a central computer

INTEL CORP57 citations96

US6247151B1Jun 12, 2001

Method and apparatus for verifying that data stored in a memory has not been corrupted

INTEL CORP50 citations96

US6157970ADec 5, 2000

Direct memory access system using time-multiplexing for transferring address, data, and control and a separate control line for serially transmitting encoded DMA channel number

INTEL CORP60 citations96

US6131127AOct 10, 2000

I/O transactions on a low pin count bus

INTEL CORP62 citations96

US6119189ASep 12, 2000

Bus master transactions on a low pin count bus

INTEL CORP65 citations96

US6012154AJan 4, 2000

Method and apparatus for detecting and recovering from computer system malfunction

INTEL CORP54 citations96

US5991841ANov 23, 1999

Memory transactions on a low pin count bus

INTEL CORP68 citations96

US5761537AJun 2, 1998

Method and apparatus for integrating three dimensional sound into a computer system having a stereo audio circuit

INTEL CORP57 citations96

US5652895AJul 29, 1997

Computer system having a power conservation mode and utilizing a bus arbiter device which is operable to control the power conservation mode

INTEL CORP68 citations96

US7024555B2Apr 4, 2006

Apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment

INTEL CORP50 citations95

US5862387AJan 19, 1999

Method and apparatus for handling bus master and direct memory access (DMA) requests at an I/O controller

INTEL CORP83 citations94

US7076802B2Jul 11, 2006

Trusted system clock

INTEL CORP23 citations93

US7051137B2May 23, 2006

Event delivery

INTEL CORP23 citations93

US7000056B2Feb 14, 2006

Method and apparatus for detecting low pin count and serial peripheral interfaces

INTEL CORP25 citations93

US6820177B2Nov 16, 2004

Protected configuration space in a protected environment

INTEL CORP33 citations93

US6754840B2Jun 22, 2004

Over-clocking detection system utilizing a reference signal and thereafter preventing over-clocking by reducing clock rate

INTEL CORP24 citations93

US6636912B2Oct 21, 2003

Method and apparatus for selecting functional space in a low pin count memory device

INTEL CORP21 citations93

US6269443B1Jul 31, 2001

Method and apparatus for automatically selecting CPU clock frequency multiplier

INTEL CORP20 citations93

US6108785AAug 22, 2000

Method and apparatus for preventing unauthorized usage of a computer system

INTEL CORP52 citations93

US5890004AMar 30, 1999

Method and apparatus for signaling power management events between two devices

INTEL CORP22 citations93

US5890012AMar 30, 1999

System for programming peripheral with address and direction information and sending the information through data bus or control line when DMA controller asserts data knowledge line

INTEL CORP46 citations93

US5664197ASep 2, 1997

Method and apparatus for handling bus master channel and direct memory access (DMA) channel access requests at an I/O controller

INTEL CORP71 citations93

US6564330B1May 13, 2003

Wakeup circuit for computer system that enables codec controller to generate system interrupt in response to detection of a wake event by a codec

INTEL CORP32 citations92

US6480965B1Nov 12, 2002

Power management method for a computer system having a hub interface architecture

INTEL CORP22 citations92

US6151654ANov 21, 2000

Method and apparatus for encoded DMA acknowledges

INTEL CORP25 citations92

US7363523B2Apr 22, 2008

Method and apparatus for controlling power management state transitions

INTEL CORP41 citations91

US5983354ANov 9, 1999

Method and apparatus for indication when a bus master is communicating with memory

INTEL CORP20 citations91

US6772245B1Aug 3, 2004

Method and apparatus for optimizing data transfer rates between a transmitting agent and a receiving agent

INTEL CORP40 citations90

US7366849B2Apr 29, 2008

Protected configuration space in a protected environment

INTEL CORP10 citations84

US7076578B2Jul 11, 2006

Race free data transfer algorithm using hardware based polling

INTEL CORP15 citations84

US6742060B2May 25, 2004

Look-up table based circuitry for sharing an interrupt between disk drive interfaces

INTEL CORP13 citations84

US6178528B1Jan 23, 2001

Method and apparatus for reporting malfunctioning computer system

INTEL CORP18 citations84

US10398130B2Sep 3, 2019

Animal control around restricted zones

INTEL CORP7 citations83

US9772180B2Sep 26, 2017

Determining device curvature in smart bendable systems

INTEL CORP4 citations82

US10349227B2Jul 9, 2019

Personal safety system

INTEL CORP8 citations81

US9984549B2May 29, 2018

Networked sensor systems and methods

INTEL CORP11 citations81

US7392415B2Jun 24, 2008

Sleep protection

INTEL CORP7 citations74

US7076669B2Jul 11, 2006

Method and apparatus for communicating securely with a token

INTEL CORP6 citations74

US7069367B2Jun 27, 2006

Method and apparatus for avoiding race condition with edge-triggered interrupts

INTEL CORP6 citations74

US7017062B2Mar 21, 2006

Method and apparatus for recovering from an overheated microprocessor

INTEL CORP8 citations74

US6938153B2Aug 30, 2005

Method and system for using internal FIFO RAM to improve system boot times

INTEL CORP6 citations74

US6581173B2Jun 17, 2003

Method and apparatus for verifying that data stored in a memory has not been corrupted

INTEL CORP5 citations74

US5708815AJan 13, 1998

DMA emulation via interrupt muxing

INTEL CORP9 citations74

US6911872B2Jun 28, 2005

Circuit and method for generating a clock signal

INTEL CORP9 citations72

Showing the top 50 of 98 patents by PatentIndex Score.

POISNER DAVID I

Patents

System for providing first type access to register if processor in first mode and second type access to register if processor not in first mode

Method and apparatus for reading initial boot instructions from a bootable device connected to the USB port of a computer system

Power management for an integrated graphics device

Method for automatic device monitoring by a central computer

Method and apparatus for verifying that data stored in a memory has not been corrupted

Direct memory access system using time-multiplexing for transferring address, data, and control and a separate control line for serially transmitting encoded DMA channel number

I/O transactions on a low pin count bus

Bus master transactions on a low pin count bus

Method and apparatus for detecting and recovering from computer system malfunction

Memory transactions on a low pin count bus

Method and apparatus for integrating three dimensional sound into a computer system having a stereo audio circuit

Computer system having a power conservation mode and utilizing a bus arbiter device which is operable to control the power conservation mode

Apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment

Method and apparatus for handling bus master and direct memory access (DMA) requests at an I/O controller

Trusted system clock

Event delivery

Method and apparatus for detecting low pin count and serial peripheral interfaces

Protected configuration space in a protected environment

Over-clocking detection system utilizing a reference signal and thereafter preventing over-clocking by reducing clock rate

Method and apparatus for mode selection in a computer system

Selecting multiple functions using configuration mechanism

Method for recovering from computer system lockup condition

Method and apparatus for selecting functional space in a low pin count memory device

Method and apparatus for automatically selecting CPU clock frequency multiplier

Method and apparatus for preventing unauthorized usage of a computer system

Method and apparatus for signaling power management events between two devices

System for programming peripheral with address and direction information and sending the information through data bus or control line when DMA controller asserts data knowledge line

Method and apparatus for handling bus master channel and direct memory access (DMA) channel access requests at an I/O controller

Wakeup circuit for computer system that enables codec controller to generate system interrupt in response to detection of a wake event by a codec

Power management method for a computer system having a hub interface architecture

Method and apparatus for encoded DMA acknowledges

Method and apparatus for controlling power management state transitions

Method and apparatus for indication when a bus master is communicating with memory

Method and apparatus for optimizing data transfer rates between a transmitting agent and a receiving agent

Protected configuration space in a protected environment

Race free data transfer algorithm using hardware based polling

Look-up table based circuitry for sharing an interrupt between disk drive interfaces

Method and apparatus for reporting malfunctioning computer system

Animal control around restricted zones

Determining device curvature in smart bendable systems

Personal safety system

Networked sensor systems and methods

Sleep protection

Method and apparatus for communicating securely with a token

Method and apparatus for avoiding race condition with edge-triggered interrupts

Method and apparatus for recovering from an overheated microprocessor

Method and system for using internal FIFO RAM to improve system boot times

Method and apparatus for verifying that data stored in a memory has not been corrupted

DMA emulation via interrupt muxing

Circuit and method for generating a clock signal